Browsing by Author "Chou, HM"

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A comparative study of electrical characteristic on sub-10-nm double-gate MOSFETs
(2005-09-01)
Li, YM
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Chou, HM
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電信工程研究所
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友訊交大聯合研發中心
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Institute of Communications Engineering
We explore the structure effect on electrical characteristics of sub-10-nm double-gate metal-oxide-semiconductor field-effect transistors (DG MOSFETs). To quantitatively assess the nanoscale DG MOSFETs' characteristics, the on/off current ratio, subthreshold swing, threshold voltage (V-th), and drain-induced barrier-height lowering are numerically calculated for the device with different channel length (L) and the thickness of silicon film (T-si). Based on our two-dimensional density gradient simulation, it is found that, to maintain optimal device characteristics and suppress short channel effects (SCEs) for nanoscale DG MOSFETs, T-si should be simultaneously scaled down with respect to L. From a practical fabrication point-of-view, a DG MOSFET with ultrathin T-si will suppress the SCE, but suffers the fabrication process and on-state current issues. Simulation results suggest that L/T-si >= 1 may provide a good alternative in eliminating SCEs of double-gate-based nanodevices.
A three-dimensional simulation of electrostatic characteristics for carbon nanotube array field effect transistors
(2005-08-01)
Li, YM
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Chou, HM
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Lee, JW
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Lee, BS
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電子物理學系
We, in this paper, study the electrostatic characteristics and the gate capacitances for carbon nanotube (CNT) array field effect transistors (FETs). The explored CNT-array FET is with three configurations of gate electrode, the top gate, the wrap around gate, and the bottom gate. Taking the pitch distance of structures and the gate length of CNT FET into consideration, a three-dimensional (3D) electrostatic simulation are performed by using an adaptive finite volume method, where different gate capacitance are calculated and compared. It is found that there is at least a 20% difference in calculating the gate capacitance between the 2D and 3D modeling and simulations. Our 3D simulation shows that a wrap around gate gives the largest gate capacitance among structures. A bottom gate possesses the weakest gate controllability. Effects of the pitch distance and the gate length on the gate capacitances of CNT-array FET are investigated. Results of the 3D electrostatic simulations can be applied to estimate the magnitude of the on-current of CNT FETs. (c) 2005 Elsevier B.V. All rights reserved.
Computer simulation of germanium nanowire field effect transistors
(2005)
Li, YM
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Chou, HM
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Lee, BS
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Lu, CS
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Yu, SM
In this paper, electrical characteristics of germanium (Ge) nanowire field effect transistors (FETs) are computationally investigated. A calibrated three-dimensional (3D) density-gradient simulation is performed to explore the electrical characteristics of Ge omega-shaped-gate FETs. The examined nanodevices are with a 70% gate coverage ratio. By evaluating the threshold voltage roll-off, the transfer characteristics, and the leakage current, our numerical results have shown that the Ge nanowire FET has potentially higher driving-capability than that of the silicon (Si) one. Due to good channel controllability of the omega-shaped-gate FET with the 70% gate coverage ratio, compared with the Si nanowire FET, the high mobility Ge nanowire FET significantly suppresses the effect of band-gap narrowing on the transport characteristics. Leakage current of the Ge nanowire FET depends upon the thickness of the gate channel film. A thinner Ge film leads to a lower leakage current. Preliminary numerical study on the Ge Nanowire FET with a propoer selection on gate material provides interesting results for the design and fabrication of high performance nanodevices in nanoelectronics era.
Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs
(2005-09-01)
Li, YM
;
Chou, HM
;
Lee, JW
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電信工程研究所
;
友訊交大聯合研發中心
In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowing, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire Fin FETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability.
Simulation of electrical characteristics of surrounding- and omega-shaped-gate nanowire FinFETs
(2004)
Tang, CS
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Yu, SM
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Chou, HM
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Lee, JW
;
Li, YM
In this paper, electrical characteristics of sub-10 not nanowire FinFETs are investigated using a three-dimensional (3D) quantum correction simulation. Two different nanowire FinFETs, surrounding-gate FinFET and omega-shaped-gate one, are simulated with density-gradient-based model and compared in terms of on/off current, turn-on resistance, gate capacitance. It is found that the characteristic difference between surrounding-gate FinFET and omega-shaped-gate FinFET with a 70% coverage is insignificant. However, the former possesses better DIBL effect than that latter with different coverage ratios. Our examination presented here is useful in the fabrication of omega-shaped nanowire FinFETs.