Browsing by Author "Chu, Li-Wei"

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A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
(2014-12-01)
Lien, Nan-Chun
;
Chu, Li-Wei
;
Chen, Chien-Hen
;
Yang, Hao-I.
;
Tu, Ming-Hsien
This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs boosted word-line (WL) for improving both read performance and write-ability. A ripple bit-line (RiBL) structure provides 30%-44% read access performance improvement and 2x-3.5x variation immunity at 0.7 V compared with the conventional hierarchical bit-line (HiBL) schemes. An adaptive data-aware write-assist (ADAWA) with VCS tracking is employed to further enhance the write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An adaptive voltage detector (AVD) with binary boosting control is used to mitigating gate electric over-stress. The design is implemented in UMC 40 nm low-power (40LP) CMOS technology. The 512 kb test chip operates from 1.5 V to 0.65 V, with maximum operation frequency of 800 MHz@1.1 V and 200 MHz@0.65 V. The measured power consumption is 0.5 mW/MHz (active) and 4.4 mW (standby) at 1.1 V, and 0.107 mW/MHz (active) and 0.367 mW (standby) at 0.65 V.
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
(2013-01-01)
Liao, Wei-Nan
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Lien, Nan-Chun
;
Chang, Chi-Shin
;
Chu, Li-Wei
;
Yang, Hao-I
This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive DataAware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 1.07GHz@1.2V and 887MHz@1.1V at 25 degrees C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25 degrees C.
Compact and Low-Loss ESD Protection Design for V-Band RF Applications in a 65-nm CMOS Technology
(2012)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.
Controlled growth of the silicide nanostructures on Si bicrystal nanotemplate at a precision of a few nanometres
(2011)
Hsin, Cheng-Lun
;
Wu, Wen-Wei
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Chu, Li-Wei
;
Hsu, Hung-Chang
;
Chen, Lih-Juann
A nanotemplate of Si bicrystal was fabricated by wafer bonding. The surface electronic energy arrangement on the surface of the Si bicrystal has been measured by scanning tunneling microscopy. The stress effect on the stepped growth of titanium silicide nanorods on Si bicrystal was observed in an ultrahigh vacuum transmission electron microscope in real time. The growth behavior of the nanorods was found to be affected by the underlying dislocation arrays significantly. For a dislocation interspacing of 3.1 nm, the dislocation arrays confined the shape of the nanoclusters and nanorods. Compared to the time of the nanorod remaining at the same length, the elongating time is more than two orders of magnitude shorter. The stepped growth behavior is attributed to the stress contour of the surface strain induced by the underlying dislocation network. This study is constructive to the basic understanding of the stress effect on the initial stage of the reaction of metals on Si and the observation may be applied to nanostructure growth for future applications and design.
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process
(2011-08-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
交大名義發表
;
National Chiao Tung University
The configurable electrostatic discharge (ESD) protection cells have been implemented in a commercial 65-nm CMOS process for 60-GHz RF applications. The distributed ESD protection scheme was modified to be used in this work. With the consideration of parasitic capacitance from I/O pad, the ESD protection cells have reached the 50-Omega input/output matching to reduce the design complexity for RF circuit designer and to provide suitable ESD protection. Experimental results of these ESD protection cells have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. These ESD protection cells can easily be used for ESD protection design in the 60-GHz RF applications, and accelerate the design cycle. (C) 2011 Elsevier Ltd. All rights reserved.
Design of Analog Pixel Memory for Low Power Application in TFT-LCDs
(2011-02-01)
Chu, Li-Wei
;
Liu, Po-Tsun
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
光電工程學系
Two types of analog memory cells realized in a 3-m low temperature polycrystalline silicon (LTPS) technology are proposed to achieve low power application for thin film transistor liquid crystal displays (TFT-LCDs). By employing the inversion signal in the storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60 to 3.16 Hz with the output decay less than 0.1 V under the input data from 1 to 4 V. To further diminish threshold voltage drop from source follower structure, a compensation technique is implemented to the proposed analog memory cells. In addition, asymmetric output voltage can be also minimized by adding a reference voltage to achieve symmetric output waveform.
Design of Bidirectional and Low Power Consumption Gate Driver in Amorphous Silicon Technology for TFT-LCD Application
(2013-02-01)
Zheng, Guang-Ting
;
Liu, Po-Tsun
;
Wu, Meng-Chyi
;
Chu, Li-Wei
;
Yang, Meng-Chuan
A new gate driver has been designed and fabricated by amorphous silicon (a-Si) technology. With utilizing four clock signals in the design of gate driver on array (GOA), the pull-up transistor has ability for both output charging and discharging, and layout size of the proposed gate driver can be narrowed for bezel panel application. Moreover, lower duty cycle of clock signals can decrease static power loss to further reduce the overall power consumption of the proposed gate driver. The scan direction of the proposed gate driver can be adjusted by switching two direct control signals to present the reversal display of image. The proposed gate driver has been successfully demonstrated in a 4.5-inch WVGA (480 x RGB x 800) TFT-LCD panel and passed reliability tests of the supporting foundry.
Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
(2012-09-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better performances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection.
Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits
(2013-03-01)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
光電工程學系
To effectively protect the millimeter-wave (MMW) circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, a dual-band ESD protection cell for 24-/60-GHz ESD protection is presented in this paper. The proposed ESD protection cell consisted of a diode, a silicon-controlled rectifier, a PMOS, and two inductors. To verify the dual-band characteristics and ESD robustness, the proposed ESD protection circuit had been applied to a 24-/60-GHz low-noise amplifier (LNA). The measurement results showed over-2-kV human-body-model ESD robustness with little performance degradation on LNA. The proposed dual-band ESD protection cell was suitable for circuit designers for them to easily apply ESD protection in the dual-band MMW circuits.
Design of ESD Protection Cell for Dual-Band RF Applications in a 65-nm CMOS Process
(2012)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
An ESD protection cell consisted of a diode, a silicon-controlled rectifier (SCR), a PMOS, and inductors was proposed for dual-band radio-frequency (RF) ESD protection. The proposed ESD protection cell was suitable for RF circuit designers for them to easily apply ESD protection in the dual-band RF circuits.
Design of ESD Protection for RF CMOS Power Amplifier with Inductor in Matching Network
(2012)
Tsai, Shiang-Yu
;
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
Due to the potential for mass production, CMOS technologies have been widely used to implement radio-frequency integrated circuits (RF ICs). Electrostatic discharge (ESD), which is one of the most important reliability issues in CMOS technologies, must be considered in RF ICs. In this work, an on-chip ESD protection design for RF power amplifier (PA) was presented. The ESD protection design consisted of an inductor in the matching network of PA. The PA with this ESD protection had been designed and fabricated in a 65-nm CMOS process. The ESD-protected PA can sustain over 4-kV human-body-mode (HBM) ESD stress, while the unprotected PA was degrated after 1-kv HBM ESD stress.
Design of Integrated Gate Driver With Threshold Voltage Drop Cancellation in Amorphous Silicon Technology for TFT-LCD Application
(2011-12-01)
Chu, Li-Wei
;
Liu, Po-Tsun
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
光電工程學系
A new integrated gate driver has been successfully designed and fabricated by amorphous silicon (a-Si) technology for a 3.8-in WVGA (800 x RGB x 480) TFT-LCD panel. With the proposed threshold voltage drop-cancellation technique, the output rise time of the proposed integrated gate driver can be substantially decreased by 24.6% for high-resolution display application. Moreover, the proposed noise reduction path between the adjacent gate drivers can reduce the layout area for slim bezel display. The transmittance brightness and contrast ratio of the demonstrated 3.8-inch panel show almost no degradation after the 500 h operation under 70 degrees C and -20 degrees C conditions.
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
(2012-03-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
光電工程學系
To effectively protect the radio-frequency (RF) circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, the silicon-controlled rectifier (SCR) devices have been used as main on-chip ESD protection devices due to their high ESD robustness and low parasitic capacitance. In this paper, an SCR device assisted with an inductor is proposed to improve the turn-on efficiency for ESD protection. Besides, the inductor can be also designed to resonate with the parasitic capacitance of the SCR device at the selected frequency band for RF performance fine tuning. Experimental results of the ESD protection design with inductor-triggered SCR in a nanoscale CMOS process have been successfully verified at 60-GHz frequency. The ESD protection design with inductor-triggered SCR has been implemented in cell configuration with compact size, which can be directly used in the RF receiver circuits. To verify the RF characteristics and ESD robustness in the RF receiver, the inductor-triggered SCR has been applied to a 60-GHz low-noise amplifier (LNA). Verified in a silicon chip, the 60-GHz LNA with the inductor-triggered SCR can achieve good RF performances and high ESD robustness.
ESD Protection Design for Radio-Frequency Integrated Circuits in Nanoscale CMOS Technology
(2013-01-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
Nanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection on circuit performances, ESD protection at input/output pads must be carefully designed. In this work, a new proposed ESD protection design has been realized in a nanoscale CMOS process. Experimental results of the test circuits have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.
ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process
(2014)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
;
Tseng, Jen-Chou
All wireless communication products must meet the reliability specifications during mass production. To prevent from electrostatic discharge (ESD) damages, the ESD protection designs must be added at all input/output pads in chip. Some ESD protection designs with low parasitic capacitance for radio-frequency (RF) applications are reviewed in this paper. Besides, a novel ESD protection design is proposed and realized in a 65nm CMOS process to protect the wideband RF circuits. In this work, diodes are used for ESD protection and inductors are used for high-frequency performance fine tuning. Experimental results of the test circuits have been successfully verified.
ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process
(2012)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
;
Jou, Chewn-Pu
To protect radio-frequency (RF) integrated circuits from electrostatic discharge (ESD) damages, silicon-controlled rectifier (SCR) devices have been used as main on-chip ESD protection devices due to their high ESD robustness and low parasitic capacitance in nanoscale CMOS technologies. In this work, the SCR device assisted with an inductor to resonate at the selected frequency band for RF performance fine tune was proposed. Besides, the inductor can be also designed to improve the turn-on efficiency of the SCR device for ESD protection. Verified in a 65-nm CMOS process, the ESD protection design with the inductor-triggered SCR for 60-GHz RF applications can achieve good RF performances and high ESD robustness.
Improving ESD Robustness of Stacked Diodes with Embedded SCR for RF Applications in 65-nm CMOS
(2014)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
Ker, Ming-Dou
;
Chu, Li-Wei
;
Tseng, Jen-Chou
To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit must be carefully designed. In this work, stacked diodes with embedded silicon-controlled rectifier (SCR) to improve ESD robustness was proposed for RF applications. Experimental results in 65-nm CMOS process show that the proposed design can achieve low parasitic capacitance, low turn-on resistance, and high ESD robustness.
Innovative Voltage Driving Pixel Circuit Using Organic Thin-Film Transistor for AMOLEDs
(2009-04-01)
Liu, Po-Tsun
;
Chu, Li-Wei
;
光電工程學系
;
顯示科技研究所
;
Department of Photonics
In this work, we propose a novel active-matrix organic light-emitting diode displays (AMOLED) pixel circuit based on organic thin-film transistor (OTFT) architecture, which consisted of four switches, one driving transistor, and a capacitor. The pentacene-based OTFT device possesses a field-effect mobility of 0.1 cm(2)/V . s, a threshold voltage of -1.5 V, subthreshold slope of 1.8 V/decade and an on/off current ratio 10(6). The resultant voltage-driving pixel circuit, named "Complementary Voltage-Induced Coupling Driving" (CVICD), is different from the current-driving scheme and can appropriately operate at low gray level for the low-mobility OTFT circuitry. The current non-uniformity less than 2.9 % is achieved for data voltage ranging from 1 to 17 V by SPICE simulation work. In addition, the new external driving method can effectively reduce the complexity of OLED pixel circuitry.
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
(2013-02-01)
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances.
Novel Shift Register Using Amorphous Silicon TFTs for Liquid Crystal Displays Application
(2011)
Chu, Li-Wei
;
Yang, Meng-Chuan
;
Liu, Po-Tsun
;
Kuo, Yi-Chun
;
光電工程學系
A new shift register has been successfully designed and integrated for a 3.8-inch WVGA (800xRGBx480) panel. With the proposed threshold voltage drop cancellation technique, output rise time can be substantially decreased by 24.6% for high resolution display application. Furthermore, the demonstrated panel shows almost no degradation after 500 hours operation.