ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process

Abstract

All wireless communication products must meet the reliability specifications during mass production. To prevent from electrostatic discharge (ESD) damages, the ESD protection designs must be added at all input/output pads in chip. Some ESD protection designs with low parasitic capacitance for radio-frequency (RF) applications are reviewed in this paper. Besides, a novel ESD protection design is proposed and realized in a 65nm CMOS process to protect the wideband RF circuits. In this work, diodes are used for ESD protection and inductors are used for high-frequency performance fine tuning. Experimental results of the test circuits have been successfully verified.