Browsing by Author "Chu, Yuan-Hua"

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40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
(2014-09-01)
Chiu, Yi-Wei
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Hu, Yu-Hao
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Tu, Ming-Hsien
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Zhao, Jun-Kai
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Chu, Yuan-Hua
This paper presents a new bit-interleaving 12T sub-threshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical V-DD to 350 mV (similar to 100 mV lower than the threshold voltage) with V-DDMIN limited by Read operation. Data can be written successfully for V-DD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 mu W at 350 mV, 25 degrees C.
A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
(2013-01-01)
Lin, Tay-Jyi
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Chien, Cheng-An
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Chang, Pei-Yao
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Chen, Ching-Wen
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Wang, Po-Hao
A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT
(2018-01-01)
Huang, Chao-Jen
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Ma, Yao-Sheng
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Yang, Wen-Hau
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Lin, Yen-Ting
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Kuo, Chun-Chieh
this paper provides a Single-Inductor Quadruple-Input--Quadruple-Output buck-boost converter to achieve maximum tracking efficiency of 99,2% due to continuous supply in one cycle. The Maximum Power Point (MPP) tracking mode and the Harvest Energy Delivering (RED) mode harvest each energy harvesting source, deliver energy to the battery and supply it to the loading system in one cycle. Each output voltage ranges from 600mV to 2.5V and the maximum output power is up to 60mW. The peak efficiency is 91.2%.
A DUAL-EDGED TRIGGERED EXPLICIT-PULSED LEVEL CONVERTING FLIP-FLOP WITH A WIDE OPERATION RANGE
(2013-01-01)
Chen, Mei-Wei
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Chang, Ming-Hung
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Wu, Pei-Chen
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Kuo, Yi-Ping
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Yang, Chun-Lin
In a multiple supply voltage system, the level converters are inserted between two different voltage domains. However, those level converters may cause the propagation delays and power consumption. In order to eliminate the overhead of level conversion, a dual-edged triggered explicitpulsed level converting flip-flop (DETEP-LCFF) with a wide operation range is proposed. It is composed of a clock pulse generator and a modified differential cascode voltage switch with pass gate (DCVSPG) latch. The clock pulse generator has the symmetric pulse triggering time and holding period helping shorten the D-Q delay. By employed diode-connected PMOS transistors and two NMOS transistor stacked below the diode PMOS transistors, the proposed DETEP-LCFF can be operated from near-threshold region to superthreshold region. It is implemented in TSMC 65nm CMOS technology. It functions correctly across all process corners with a wide input voltage range, from 400mV to 1V. The proposed LCFF has a minimum D-Q delay of 781 ps, a setup time of 610ps, and a power dissipation of 2.3 mu W when the input voltage is OAV.
A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications
(2015-08-01)
Chang, Chia-Wen
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Chu, Yuan-Hua
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Jou, Shyh-Jye
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a cell-based all-digital phase-locked loop (ADPLL) with hierarchical gated digitally controlled oscillator (G-DCO) for low voltage operation, wide frequency range as well as low-power consumption. In addition, a new time-domain hierarchical frequency estimation algorithm (HFEA) for frequency acquisition is proposed to estimate the output frequency in 1.5M(F) (M-F = 3 in this paper) cycles and this fast lock-in time is suitable to the dynamic voltage frequency scaling (DVFS) systems. A hierarchical G-DCO is proposed to work at low supply voltage to reduce the power consumption and at the same time to achieve wide frequency range and precise frequency resolution. The core area of the proposed ADPLL is 0.02635 mm(2). In near-threshold region (V-DD = 0.36 V), the proposed ADPLL only dissipates 68.2 mu W and has a rms period jitter of 1.25% UI at 60 MHz output clock frequency. Under 0.5 V V-DD operation, the proposed ADPLL dissipates 404.2 mu W at 400 MHz. The fast lock-in time of 4.489 mu s and the low jitter performance below 0.5% UI at 400 MHz output clock frequency in the proposed ADPLL are suitable in event-driven or DVFS applications.
A Sustainable Soil Energy Harvesting System With Wide-Range Power-Tracking Architecture
(2019-10-01)
Ou, I-Che
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Yang, Jia-Ping
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Liu, Chia-Hung
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Huang, Kai-Jie
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Tsai, Kun-Ju
For wide-range deployment of wireless sensing nodes in power- and size-constrained Internet of Things applications, self-sustaining wireless sensors without batteries are needed. The energy supply for these ubiquitous sensing devices should harness environmental energy sources to avoid frequent battery replacement and pollution. This paper presents a new soil energy harvesting system with a power management integrated circuit (IC) for wide-range maximum power point tracking (MPPT). The output power of a soil energy cell varies widely according to the soil moisture and soil contents. To extract the maximum amount of energy from the soil, high-efficiency power management with adaptive dc-dc conversion ratios and an MPPT mechanism is essential. The proposed system is implemented with a high-efficiency dc-dc converter IC in a 0.18-mu m CMOS process. The design achieves a peak tracking efficiency of 90.5% in the throughput power range from 56 mu W to 1 mW at an output voltage of 3 V and system efficiency exceeding 65% over an input resistance range of the soil energy source; the peak system efficiency is 73.9%. A demonstration was undertaken of the soil energy harvesting system lighting an LED array without any chemical batteries.
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques
(2016-04-01)
Chang, Chia-Wen
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Lo, Kai-Yu
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Ibrahim, Hossameldin A.
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Su, Ming-Chiuan
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Chu, Yuan-Hua
This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.
A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy Extraction
(2018-01-01)
Ou, I-Che
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Yang, Jia-Ping
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Liu, Chia-Hung
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Huang, Kai-Jie
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Tsai, Kun-Ju
This paper presents a capacitive DC-DC converter with adaptive DC-DC conversion ratios and maximum power point tracking (MPPT) for soil and solar energy extraction. To overcome the varying input power ranges of the soil/solar energy sources, a two-dimension power tracking loop with time-based current slope detection was employed. The design was fabricated in a 0.18 mu m CMOS process, achieving >80% efficiency in a throughput power range of 360 mu W to 25mW in the soil mode and from 400 mu W to 10mW in the solar mode while the peak system efficiency is 89.5%.
All Digitally Controlled Linear Voltage Regulator with PMOS Strength Self-Calibration for Ripple Reduction
(2015)
Kuo, Yi-Ping
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Huang, Po-Tsang
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Wu, Chung-Shiang
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Liang, Yu-Jie
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Chuang, Ching-Te
In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best ( lowest) FOM of 0.76 pA.s can be realized.
An All-Digital Power Management Unit with 90% Power Efficiency and ns-order Voltage Transition Time for DVS Operation in Low Power Sensing SoC Applications
(2015)
Wu, Chung-Shiang
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Lin, Kai-Chun
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Kuo, Yi-Ping
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Chen, Po-Hung
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Chu, Yuan-Hua
A 1V similar to 1.2V battery input, 0.4V similar to 0.6V output low-power all-digital power management unit (PMU) composed of a high-efficiency digital buck converter (DBC) and a fast-transient digital low drop-out (DLDO) regulator is developed for energy-efficient SoC applications. A fully integrated 2-to-1 switchedcapacitor dc-dc converter is combined together to reduce the quiescent current of digital control circuits. The digital pulse width modulation (DPWM) with clock frequency gating further reduces the power consumption of buck converter in steady state. From experiment results, the peak power efficiency of the proposed buck converter is 90% with an output power range of 30 mu W to 3mW and the peak current efficiency of DLDO is 98.8% at 5mW. Moreover, the proposed DLDO achieves 92ns/ 130ns transition time in 60mV voltage step to dynamically scaling the voltage of supply voltage in digital circuits. This chip is designed and fabricated in 65nm CMOS process for verification.
An Ultra-Low Power Interface CMOS IC Design for Biosensor Applications
(2012)
Hu, Weibo
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Liu, Yen-Ting
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Das, Vighnesh
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Schecht, Cliff
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Tam Nguyen
This paper presents a design example of an ultra-low power single-channel analog front-end (AFE) integrated circuits (IC) and system for biomedical sensing applications. The 0.18-mu m CMOS AFE IC design includes a low noise instrumentation amplifier (INA), a low-pass filter (LPF), a variable gain amplifier (VGA), and a successive approximation register (SAR) analog-to-digital converter (ADC). The AFE IC architecture is analyzed on the system level to minimize total power consumption with high integration and optimized for an ECG sensing system. SPICE simulations of the AFE IC channel validate the ultra-low power IC design methodology for heartbeat detection with less than 1 mu A/channel.
An Ultra-Low Voltage Hearing Aid Chip using Variable-Latency Design Technique
(2014-01-01)
Chang, Kuo-Chiang
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Luo, Shien-Chun
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Huang, Ching-Ji
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Liu, Chih-Wei
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Chu, Yuan-Hua
This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 mu W at 0.5V and 6 MHz.
Batteryless 275mV Startup Single-Cell Photovoltaic Energy Harvesting System for Alleviating Shading Effect
(2013-01-01)
Huang, Chao-Jen
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Su, Yi-Ping
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Chen, Ke-Horng
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Huang, Li-Ren
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Chu, Fang-Chih
without any batteries, a low input voltage converter is presented for a single-cell (SC) photovoltaic (PV) energy harvesting to alleviate the energy degradation due to shading effect. The proposed low voltage startup (LVS) circuit with low input voltage of 275 mV and less than 840 ms startup time achieves high voltage conversion ratio to supply a high accuracy bandgap reference. Experimental results show the maximum power throughput is up to 6 mW and the quiescent power is less than 650 mu W with integrated two buck-boost converters and two boost converters. The peak efficiency of the boost converter can be up to 75.8% for ultra-low voltage hearing aid systems.
Batteryless 275mV Startup Single-Cell Photovoltaic Energy Harvesting System for Alleviating Shading Effect
(2013-01-01)
Huang, Chao-Jen
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Su, Yi-Ping
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Chen, Ke-Horng
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Huang, Li-Ren
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Chu, Fang-Chih
without any batteries, a low input voltage converter is presented for a single-cell (SC) photovoltaic (PV) energy harvesting to alleviate the energy degradation due to shading effect. The proposed low voltage startup (LVS) circuit with low input voltage of 275 mV and less than 840 ms startup time achieves high voltage conversion ratio to supply a high accuracy bandgap reference. Experimental results show the maximum power throughput is up to 6 mW and the quiescent power is less than 650 mu W with integrated two buck-boost converters and two boost converters. The peak efficiency of the boost converter can be up to 75.8% for ultra-low voltage hearing aid systems.
Essential factors that affect bioelectricity generation byRhodopseudomonas palustrisstrainPS3in paddy soil microbial fuel cells
(1970-01-01)
Liu, Chia-Hung
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Lee, Sook-Kuan
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Ou, I-Che
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Tsai, Kun-Ju
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Lee, Yu
A plant-associated phototrophic bacterium,R. palustrisstrain PS3, was inoculated into a soil-based MFC to generate electricity. We evaluated the performance of this soil-based microbial fuel cell (MFC) and elucidated the essential factors that contributed to power generation. PS3 showed the potential to enhance power generation, especially when the apparatus was operated in a sealed chamber with illumination.We deduced that the improved power performance was due to the enhanced electron transport through the living electrode that was grown as a PS3 biofilm via photoheterotrophic metabolism. In addition, we suggested that the interplay between phototrophic fixation of ambient CO(2)and anaerobic oxidation of ferrous iron in soil was also involved in the increased power output. We implemented CMOS (complementary metal-oxide-semiconductor) technology with the soil-based MFC to harvest energy in a more efficient and stable manner. The above system is expected to provide a potentially low-cost and low-energy system with a high power conversion efficiency for practical applications in the future.
Invited: Wireless sensor nodes for environmental monitoring in Internet of Things
(2016)
Lu, Ting-Chou
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Huang, Li-Ren
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Lee, Yu
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Tsai, Kun-Ju
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Liao, Yu-Te
This paper presents a self-sustainable landslide surveillance system that detects hazardous water content level in soils and provides real-time landslide warnings to residents, without requiring wired electricity transmission. A self-powered soil water content sensor was applied as the trigger of alert event. It solves the energy supply problem by an environmental interrupt mechanism, which wakes up the sensor and communication circuits in a sensing node only when the water content in monitored soils exceeds a certain threshold, and thus completely eliminates the need for an ALS node to periodically wake up, sense and communicate. By tightly integrating energy harvesting, environment sensing and circuit wake-up, it may well be the most energy-efficient landslide surveillance system designed to monitor water content in soils in the world.
Invited: Wireless sensor nodes for environmental monitoring in Internet of Things
(2016)
Lu, Ting-Chou
;
Huang, Li-Ren
;
Lee, Yu
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Tsai, Kun-Ju
;
Liao, Yu-Te
This paper presents a self-sustainable landslide surveillance system that detects hazardous water content level in soils and provides real-time landslide warnings to residents, without requiring wired electricity transmission. A self-powered soil water content sensor was applied as the trigger of alert event. It solves the energy supply problem by an environmental interrupt mechanism, which wakes up the sensor and communication circuits in a sensing node only when the water content in monitored soils exceeds a certain threshold, and thus completely eliminates the need for an ALS node to periodically wake up, sense and communicate. By tightly integrating energy harvesting, environment sensing and circuit wake-up, it may well be the most energy-efficient landslide surveillance system designed to monitor water content in soils in the world.
Multiple Output Switched Capacitor DC-DC Converter with Capacitor Sharing for Sensor-Fusion Platforms
(2016)
Liang, Yu-Jie
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Chen, Po-Ilung
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Lu, Hung-Pin
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Chu, Yuan-Hua
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Hwang, Wei
In this paper, a multiple output switched capacitor (SC) DC-DC converter with capacitor sharing technique is proposed for event-driven energy-efficient sensor-fusion platforms. The converter is able to convert 1.2V supply voltage to five different output voltages ranging from 0.44V to 2.2V to power different building blocks in the system. A part of the flying capacitor can be shared between five SC cells according to the loading condition to reduce the chip area. With capacitor sharing concept, 36% of on-chip metal-insulator-metal (MIM) capacitor can be reduced. The proposed switched capacitor DC-DC converter is implemented by TSMC 90nm CMOS process. The simulation results show the converter achieves 80% maximum conversion efficiency with less than 20mV output ripple.
Parallel Architecture Core (PAC)-the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools
(2011-03-01)
Chang, David Chih-Wei
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Lin, Tay-Jyi
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Wu, Chung-Ju
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Lee, Jenq-Kuen
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Chu, Yuan-Hua
In order to develop a low-power and high-performance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003. A VLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed & ping-pong register organization and variable-length VLIW encoding, to a highly-configurable soft IP with several successful silicon implementations. A complete toolchain with an optimizing C compiler has also been developed for PACDSP. A dual-core PAC SoC has been designed and fabricated, which consists of a PACDSP core, an ARM9 core, scratchpad memories, and various on-chip peripherals, to demonstrate the outstanding performance and energy efficiency for multimedia processing such as the real-time H.264 codec. The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (DVFS).
Self-Sustaining Soil Electrical Conductance Measurement Using a DC-DC Power Converter
(2019-11-15)
Ou, I-Che
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Tsai, Kun-Ju
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Chu, Yuan-Hua
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Liao, Yu-Te
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電機工程學系
This paper presents a self-sustained soil electrical conductivity (soil-EC) sensing IC. The sensing system harvests energy and measures the conductivity of the soil simultaneously using the proposed wide-range DC-DC converter. The power management circuits must accommodate the wide variations of the soil conductivity at varying power levels. The time-domain current sensing mechanism, which is embedded in the DC-DC converter, is employed to measure conductivity. Also, the digital codes are recorded and control the converter for achieving maximal power extraction and maintaining high conversion efficiency. The self-sustained soil-EC monitoring IC was fabricated using 0.18-mu m CMOS technology. The range of the input voltage from a soil cell is from 0.8 to 1 V when carbon and zinc electrodes are used. The design achieves a tracking efficiency of 98% over an input range of 416-5000 mu W, a throughput power range from 150 mu W to 4.32 mW, and a peak system conversion efficiency of 88%, while the regulated voltage is about 1.7-1.8 V. The design can also measure the soil EC from 0.114 to 0.744 mS/cm in a resolution of 0.00568 mS/cm per bit.