Browsing by Author "Chuang, CH"

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Effects in carrier dynamics of Isolectronic In doped in GaN films grown by metalorganic vapor phase epitaxy
(2000)
Huang, HY
;
Shu, CK
;
Lin, WC
;
Liao, KC
;
Chuang, CH
Time-resolved photoluminescence spectra were used to characterize isoelectronically doped GaN:In films. Our results indicate that the recombination lifetime of donor-bound-exciton transition of pure GaN exhibits strong dependence on temperature. When In is doped into GaN, the recombination lifetime decreases sharply from 68 ps to 30 ps, irregardless of measured temperature and In doping concentration. The cause for this appearance is not clear at present. It might be related to the isoelectronic In impurity itself in GaN, which creates shallow energy levels that predominate the recombination process.
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
(2002-08-01)
Ker, MD
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new electrostatic discharge (ESD) protection circuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35-mum CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original similar to2 kV to >8 kV by using this proposed ESD protection circuit.
ESD failure mechanisms of analog I/O cells in 0.18-mu m CMOS technology
(2006-03-01)
Ker, MD
;
Chen, SH
;
Chuang, CH
;
電機學院
;
College of Electrical and Computer Engineering
Different electrostatic discharge (ESD) protection schemes have been investigated to find the optimal ESD protection design for an analog input/output (I/O) buffer in 0.18-mu m 1.8- and 3.3-V CMOS technology. Three power-rail ESD clamp devices were used in power-rail ESD clamp circuits to compare the protection efficiency in analog I/O applications, namely: 1) gate-driven NMOS; 2) substrate-triggered field-oxide device, and 3) substrate-triggered NMOS with dummy gate. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable designs for the analog I/O buffer in the 0.18-mu m CMOS process. Each ESD failure mechanism was inspected by scanning electron microscopy photograph in all the analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic n-p-n bipolar transistor between the ESD clamp device and the guard ring structure was triggered to discharge the ESD current and cause damage under ND-mode ESD stress.
ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology
(2005-05-01)
Ker, MD
;
Chuang, CH
;
Lo, WY
;
電機學院
;
College of Electrical and Computer Engineering
One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18 mu m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I-t2) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.
ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration
(2001)
Ker, MD
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
ESD protection circuits with novel MOS-bounded diode structures
(2002)
Ker, MD
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On-chip ESD protection circuits realized with novel diode structures without the field-oxide boundary across the p/n junction are proposed. A PMOS (NMOS) is especially inserted into the diode structure to form the PMOS-bounded (NMOS-bounded) diode, which is used to block the field oxide isolation across the p/n junction in the diode structure. Without the field oxide boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can sustain much higher ESD stress, especially under the reverse-biased condition. Such PMOS-bounded and NMOS-bounded diodes are fully process-compatible to general CMOS processes without additional process modification or mask layers. The ESD protection circuits designed by such new diodes with different junction perimeters have been successfully verified in a 0.35-mum CMOS process.
ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
(2002)
Ker, MD
;
Chuang, CH
;
Hsu, KC
;
Lo, WY
;
電子工程學系及電子研究所
A substrate-triggered technique is proposed to improve ESD Protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3.3V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-mum salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased similar to 65% by this substrate-triggered design.
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process
(2001)
Ker, MD
;
Chuang, CH
;
Lo, WY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-mum salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level, The layout of I/O cell can be drawn more compactly, but still to provide deep-submicron CMOS IC's with higher ESD robustness.
Microstructural evolution and formation of highly c-axis-oriented aluminum nitride films by reactively magnetron sputtering deposition
(2005-04-01)
Liu, WJ
;
Wu, SJ
;
Chen, CM
;
Lai, YC
;
Chuang, CH
Highly (0 0 2) c-axis-oriented AlN films have been successfully deposited on Ti/Si substrates using reactive magnetron radio frequency (RF) sputtering deposition and ideal AlN films could be obtained by fine-tuning the parameters at pressure 5Pa, temperature of 250 degrees C, and N-2 ratio 85%. The detailed layer-by-layer microstructure of AlN films deposited on Ti/Si substrate consists of TiO2 thin film, amorphous layer without Al2O3 particles, transition layer, and the columnar (0 0 2) e-axis preferred orientation layer. AlN films possessing a higher deposition rate to form an amorphous layer in the initial deposition stage will result in the lower deposition rate to form following transition and columnar preferred orientation textures. Therefore, we strongly suggest adopting a two-step deposition method, that is, use lower deposition rate to form preferred orientation layers and then a higher deposition rate to form preferred orientation textures. (c) 2004 Elsevier B.V. All rights reserved.
MOS-bounded diodes for on-chip ESD protection in a 0.15-mu m shallow-trench-isolation salicided CMOS process
(2003)
Ker, MD
;
Lin, KH
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Novel diode structures without the shallow trench isolation (STI) across the p/n junction for ESD protection in a 0.15-mum CMOS process are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the STI isolation across the p/n junction in the diode structure. Without the STI boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can provide more effective protection to the internal circuits, as compared to the other diode structures under reverse-biased condition. Such PMOS-bounded and NMOS-bounded dodes are fully process-compatible to general CMOS processes without additional process modification or mask layers.
MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process
(2005-03-01)
Ker, MD
;
Lin, KH
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New diode structures without the field-oxide boundary across the p/n junction for ESD protection are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the field oxide isolation across the p/n junction in the diode structure. The proposed N(P)MOS-bounded diodes can provide more efficient ESD protection to the internal circuits, as compared to the other diode structures. The N(P)MOS-bounded diodes can be used in the I/O ESD protection circuits, power-rail ESD clamp circuits, and the ESD conduction cells between the separated power lines. From the experimental results, the human-body-model ESD level of ESD protection circuit with the proposed N(P)MOS-bounded diodes is greater than 8 kV in a 0.35-mu m CMOS process.
On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
(2004-10-01)
Ker, MD
;
Lin, KH
;
Chuang, CH
;
電機學院
;
College of Electrical and Computer Engineering
A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-mum salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.
Photoluminescence and photoluminescence excitation studies of as-grown and P-implanted GaN: On the nature of yellow luminescence
(2002-05-06)
Huang, HY
;
Chuang, CH
;
Shu, CK
;
Pan, YC
;
Lee, WH
We have studied optical and electronic properties of isoelectronic P-implanted GaN films grown by metalorganic chemical vapor phase epitaxy. After rapid thermal annealing, a strong emission band around 430 nm was observed, which is attributed to the recombination of exciton bound to isoelectronic P-hole traps. From the Arrhenius plot, the hole binding energy of similar to180 meV and the exciton localization energy of 28 meV were obtained. According to first-principle total-energy calculations, the implantation process likely introduced N(I) and P-related defects. By using photoluminescence excitation technique, we found that the P-implantation-induced localized states not only increase the yellow luminescence but also suppress the transitions from the free carriers to deep levels. (C) 2002 American Institute of Physics.
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
(2002-06-01)
Ker, MD
;
Chuang, CH
;
電機學院
;
College of Electrical and Computer Engineering
A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using the thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35-mum CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 mum can be obviously improved from the original similar to2 kV to be greater than 8 kV by this SNTSCR device with a device dimension of only 60 mum/0.35 mum.
The electronic structure and optical properties of phosphorus implanted GaN films
(2000)
Shu, CK
;
Lee, WH
;
Huang, HY
;
Chuang, CH
;
Chen, WK
We have studied optical and electronicc transition properties of GaN layers grown by MOCVD which are implanted by isoelectronic impurities of phosphorus (P). The P-implanted samples were treated by rapid thermal annealing to recover implantation-induced damages. A strong emission band around 430 nm were observed in P-implanted sample due to the recombination of bound exciton to P-hole isoelectronic traps. From the Arrhenius plot, the hole binding energy about 180 meV localized at the P-isoelectronic trap and the exciton localization energy of 28 meV were obtained. According to first-principle total-energy calculations, we suggest that the implantation likely induces N-I or P-related defects. From the PLE, we found that the absorption by band-to-band and shallow donors dominates the yellow luminescence (YL) and the implantation of P has induced localized states that not only increase the YL but also suppress the transition from the free electron-hole pairs to the deep-levels.
Time-resolved photoluminescence study of isoelectronic In-doped GaN films grown by metalorganic vapor-phase epitaxy
(2000-05-29)
Huang, HY
;
Shu, CK
;
Lin, WC
;
Chuang, CH
;
Lee, MC
Time-resolved photoluminescence spectra were used to characterize isoelectronically doped GaN:In films. Our results indicate that the recombination lifetime of the donor-bound-exciton transition of undoped GaN exhibits a strong dependence on temperature. When In is doped into the film, the recombination lifetime decreases sharply from 68 to 30 ps, regardless of the measured temperature and In source flow rate. These observations might be related to the isoelectronic In impurity itself in GaN, which creates shallow energy levels that predominate the recombination process. (C) 2000 American Institute of Physics. [S0003- 6951(00)02622-X].