Browsing by Author "Chung, Ching-Che"

Now showing 1 - 12 of 12

A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications
(2011-08-01)
Chung, Ching-Che
;
Yu, Jui-Yuan
;
Jang, Shiou-Ru
;
Lee, Chen-Yi
;
電機工程學系
This work provides an all-digital smart temperature sensor with dual-mode transceiver chipset for wireless body area network (WBAN). The measurement results show that the proposed temperature sensor achieves a maximum temperature error < 0.6A(0)C within the range from 20A(0)C to 50A(0)C. And a phase-frequency tunable clock generator (PFTCG) is designed with frequency and phase tuning capability on the fly. This chip is manufactured on a standard 90 nm CMOS process. The supply voltage to the chip core is globally applied at 0.5 V with 12 power-domain partitions for sleep-active and voltage-scaling management. The transceiver chipset provides maximum 7 Mbps data rate, resulting in 97.7% efficiency improvement in baseband circuit processing.
A fast-lock-in ADPLL with high-resolution and low-power DCO for SoC applications
(2006)
Sheng, Duo
;
Chung, Ching-Che
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a fast-lock-in all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by Hardware Description Language (HDL). The proposed ADPLL uses a novel 2-level flash time-to-digital converter (TDC) to lock in within 2 reference clock cycles. The novel digitally controlled oscillator (DCO) achieves high-resolution with 0.93ps resolution and can extend the controllable range easily. In addition to high-resolution, the power consumption of the proposed DCO can be lowered as 110 mu W(@200MHz). The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP), making it very suitable for System-On-Chip (SoC) applications as well as system-level power management
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications
(2011-06-01)
Sheng, Duo
;
Chung, Ching-Che
;
Lee, Chen-Yi
;
電機工程學系
;
Department of Electrical and Computer Engineering
In this paper, a novel portable and all-digital spread spectrum clock generator (ADSSCG) suitable for system-on-chip (SoC) applications with low-power consumption is presented. The proposed ADSSCG can provide flexible spreading ratios by the proposed rescheduling division triangular modulation (RDTM). Thus it can provide different EMI attenuation performance for various system applications. Furthermore, the proposed ADSSCG employs a low-power digitally controlled oscillator (DCO) to save overall power consumption significantly. Measurement results show that power consumption of the proposed ADSSCG is 1.2 mW (@54 MHz), and it provides 9.5 dB EMI reductions with 1% spreading ratio. Besides, the proposed ADSSCG has very small chip area as compared with conventional SSCGs which often required large on-chip loop filter capacitors. In addition, the proposed ADSSCG is implemented only with standard cells, making it easily portable to different processes and very suitable for SoC applications.
A Low-Power DCO Using Interlaced Hysteresis Delay Cells
(2012-10-01)
Yu, Chien-Ying
;
Chung, Ching-Che
;
Yu, Chia-Jung
;
Lee, Chen-Yi
;
電機工程學系
This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-fine architecture with binary-weighted delay stages is applied for the delay range and resolution optimization. The coarse-tuning stage of the DCO uses the interlaced hysteresis delay cell, which is power and area efficient, as compared with conventional delay cells. The glitch protection synchronous circuit makes the DCO easily controllable without generating glitches. A demonstrative all-digital phase-locked loop using the DCO is fabricated in a 90-nm CMOS process with an active area of 0.0086 mm(2). The measured output frequency range is 180-530 MHz at the supply of 1 V. The power consumption are 466 and 357 mu W at 480- and 200-MHz output, respectively.
A symbol-rate timing synchronization method for low power wireless OFDM systems
(2008-09-01)
Yu, Jui-Yuan
;
Chung, Ching-Che
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work addresses power reduction and performance improvement for wireless orthogonal frequency-division multiplexing (OFDM) systems using a dynamic sample-timing controller (DSTC) and phase-tunable clock generator (PTCG). The receiver, applying the proposed DSTC algorithm, searches for the optimal sampling phase at the symbol rate, instead of the Nyquist rate (or higher), to reduce the extra power consumed in high-rate operations. The proposed PTCG circuits provide the desired clock phase for optimum sampling to improve system performance. Both the DSTC and the PTCG are evaluated in a multibandt OFDM (MB-OFDM) ultra-wide-band system. Simulation results indicate that the overall system performance is improved by 1.7-dB signal-to-noise ratio at a packet error rate of 8% and the total baseband power is reduced by 40%.
An All Digital Spread Spectrum Clock Generator with Programmable Spread Ratio for SoC Applications
(2008)
Sheng, Duo
;
Chung, Ching-Che
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a programmable all-digital spread spectrum clock generator (ADSSCG) suitable for System-On-Chip (SoC) applications with ultra-low-power capability is presented. Based on the timing constraint of system, the programmable ADSSCG can provide the suitable frequency spread ratio to obtain the optimal combination of timing deviation and EMI reduction for system applications. Besides, the proposed ADSSCG employs an ultra-low-power digitally controlled oscillator (DCO) to save overall power consumption to 560 mu W (@400MHz) and the peak EMI power reduction is large than 25dB. In addition, the proposed ADSSCG can be implemented only with standard cells; as a result, the area can be saved without any passive component, and making it easily portable to different processes and very suitable for SoC applications.
An all-digital delay-locked loop for DDR SDRAM controller applications
(2006)
Chung, Ching-Che
;
Chen, Pao-Lung
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an all-digital Delay-Locked Loop (DLL) for DDR SDRAM controller applications. The presented all-digital, cell-based, DLL-based five-phase multi-phase clock generator can generate the required fixed timing delay (tSD) for DDR SDRAM controller to capture the output data (DQ) correctly. The proposed DLL-based multi-phase clock generator architecture can lock to the harmonic of input clock period and still get a correct multi-phase clock output. Hence the design challenges to build a high resolution delay line with minimum intrinsic delay can be reduced. Simulation results and chip measurement results show that the proposed DLL can generate desired tSD delay with error < 7.6%). The power consumption of the proposed DLL is 4.1 mW (at DDR-200) and is 9.0mW (at DDR-400).
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems
(2007)
Yu, Jui-Yuan
;
Chen, Juinn-Ting
;
Yang, Mei-Hui
;
Chung, Ching-Che
;
Lee, Chen-Yi
An all-digital clock generator is designed to enable the clock phase and frequency tuning dynamically during the wireless communications system is in operation. This phase-frequency tunable clock generator (PFTCG) provides 8 clock phases for selection and enables the ADC circuits sampling signals with lower frequency and better sampling phase, resulting in lower power consumption. The PFTCG provides the frequency tuning range +/- 150ppm centered at 5MHz, resulting in high performance due to smaller sampling clock offset. This PFTCG is simulated under the wireless body area network system, and shows a 6.3dB SNR improvement at BER=1 e(-3), and the. hardware is simulated with power 77.56 mu M in the standard process 90nm CMOS technology.
An all-digital phase-locked loop with high-resolution for SoC applications
(2006)
Sheng, Duo
;
Chung, Ching-Che
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a very high-resolution all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by Hardware Description Language (HDL). The proposed ADPLL uses a novel digitally controlled oscillator (DCO) to achieve 1.06ps resolution and the proposed DCO can extend the controllable range easily. The dead zone of the proposed phase/frequency detector (PFD) is 5ps. The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP) block, making it very suitable for System-On-Chip (SoC) and system-level applications.
An ultra-low-power and portable digitally controlled oscillator for SoC applications
(2007-11-01)
Sheng, Duo
;
Chung, Ching-Che
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with conventional approaches. Besides, the proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Measurement results show that power consumption of the proposed DCO can be improved to 140 mu W (@200 MHz) with 1.47-ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.
Design of a 125 mu W, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications
(2006)
Liu, Tsu-Ming
;
Chung, Ching-Che
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Lee, Chen-Yi
;
Lin, Ting-An
;
Wang, Sheng-Zen
A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18 mu m CMOS [1]. The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps are achieved at 1.15MHz with power dissipation of 108 mu W and 125 mu W respectively at 1V supply voltage.
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications
(2010-05-10)
Sheng, Duo
;
Chung, Ching-Che
;
Lee, Chen-Yi
;
電機工程學系
;
Department of Electrical and Computer Engineering
A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90 degrees phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3 degrees at 400 MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides the suitable phase shift of control signals for DDR interface where precise control is the key to reliable high-performance operation. Besides, the cell-based implementation makes it easy to target a variety of technologies as a soft silicon intellectual property (IP).