An all-digital delay-locked loop for DDR SDRAM controller applications

Abstract

This paper presents an all-digital Delay-Locked Loop (DLL) for DDR SDRAM controller applications. The presented all-digital, cell-based, DLL-based five-phase multi-phase clock generator can generate the required fixed timing delay (tSD) for DDR SDRAM controller to capture the output data (DQ) correctly. The proposed DLL-based multi-phase clock generator architecture can lock to the harmonic of input clock period and still get a correct multi-phase clock output. Hence the design challenges to build a high resolution delay line with minimum intrinsic delay can be reduced. Simulation results and chip measurement results show that the proposed DLL can generate desired tSD delay with error < 7.6%). The power consumption of the proposed DLL is 4.1 mW (at DDR-200) and is 9.0mW (at DDR-400).