Browsing by Author "Chung, SS"

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A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's
(1999-07-01)
Chung, SS
;
Yang, JJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N-it) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N-it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N-it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices.
A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
(1998-11-01)
Yih, CM
;
Cheng, SM
;
Chung, SS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N-it) and oxide trapped charge (Q(ox)), were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N-it and Q(ox) has thus been proposed, Furthermore, the individual contributions of N-it and Q(ox) to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I-G (max). Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and Flash EEPROM devices.
A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
(1998-11-01)
Yih, CM
;
Cheng, SM
;
Chung, SS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N-it) and oxide trapped charge (Q(ox)), were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N-it and Q(ox) has thus been proposed, Furthermore, the individual contributions of N-it and Q(ox) to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I-G (max). Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and Flash EEPROM devices.
A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles
(1997)
Chung, SS
;
Yih, CM
;
Cheng, SM
;
Liang, MS
;
交大名義發表
A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering
(2005)
Chung, SS
;
Liu, YR
;
Wu, SJ
;
Lai, CS
;
Liu, YC
In this paper, the difference in degradation mechanism for different substrate engineered CMOS devices has been reported for the first time. These two different substrate engineering includes hybrid substrate engineering, with (100) and (110) orientations, and strained-Si devices. Different mechanisms are responsible for these two different mobility enhancement schemes. For strained-Si devices, it shows that the dominant mechanism for HC(Hot Carrier) and NBT (Negative Bias Temperature) degradations is attributed to the lateral electric field resulting from the mobility enhancement. While for (110)/(100) substrate engineered devices, the dominant mechanism is due to the dangling bond of the surface. In other words, for (I I 0)/(l 00) substrate, the device degradation is weakly dependent on the mobility enhancement while largely dependent on the bond strength. Finally, the difference in temperature dependence of HC and NBT has also been observed for both strained-Si and (110)/(100) substrate devices. Sophisticated measurement techniques, charge pumping (CP) and gated-diode (GD) measurement, have been employed to understand these device mechanisms. These results provide a guideline for the device design and the understanding of related reliabilities in the popular strained-Si and hybrid substrate technology CMOS devices.
A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFET's
(1996-01-01)
Lee, RGH
;
Su, JS
;
Chung, SS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Previous studies showed that simultaneous determination of the interface states (N-it) and oxide-trapped charges (Q(ox)) in the vicinity of the drain side in MOS devices was rather difficult, A new technique which allows a consistent characterization of the spatial distributions of both hot-carrier-induced N-it and Q(ox) is presented, Submicron LDD n-MOS devices were tested and charge pumping measurements were performed, The spatial distributions of both N-it and Q(ox) have been justified by two-dimensional (2-D) device simulation of the I-V characteristics for devices before and after the stress. Comparison of the drain current characteristics between simulation and experiment shows very good agreement. Moreover, results show that fixed-oxide charge effect is less pronounced to the device degradation for devices.
A new observation of the germanium outdiffusion effect on the hot carrier and NBTI reliabilities in sub-100nm technology strained-Si/SiGe CMOS devices
(2005)
Chung, SS
;
Liu, YR
;
Yeh, CF
;
Wu, SR
;
Lai, CS
In this paper, the evidence of SiGe layer induced trap generation and its correlation with enhanced degradation in strained-Si/SiGe CMOS devices have been reported for the first time. First, a new two-level charge pumping(CP) curve has been demonstrated to identify the Ge out-diffusion effect. Secondly, enhanced degradation in strained-Si devices has been clarified based on experimental results. Both n- and p-MOSFE's exhibit different extent of HC degradation effect. This is attributed to the difference in their mobility enhancement as well as additional traps coming from the Si/SiGe interface. Finally, temperature dependence of HC and NBTI has been examined for both strained-Si and bulk devices. Sophisticated measurement techniques, charge pumping and gated-diode (GD) measurements, have been employed to understand the generated interface traps. Results show that strained-Si device is less sensitive to the temperature and has a chance for better NBTI reliability if we have a good control of the strained-Si/SiGe interface, such as through low temperature gate oxide process or better S/D junction formation.
A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices
(2001)
Chung, SS
;
Chen, SJ
;
Yang, WJ
;
Yang, JJ
;
電子工程學系及電子研究所
In this paper, we present new results on the width dependent hot-carrier (HC) degradation for shallow-trench-isolated (STI) CMOS devices. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. New models and mechanisms are proposed to explain the width dependent degradation for both n-channel and p-channel MOSFET's, where new monitors are developed for both types of devices respectively. In fi-MOSFET's, the interface state generation at the STI-edge is enhanced for narrow width device. However, for p-MOSFET's, a two-dimensional channel shortening model is introduced. The channel shortening induced oxide damage is the dominant mechanism for the drain current degradation. Both are found to be strongly related to the mechanical stress on the border of the trench. This is a very crucial issue for the present and future CMOS ULSI using STI technologies.
A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles
(1999-09-01)
Chung, SS
;
Yih, CM
;
Cheng, SM
;
Liang, MS
;
電子工程學系及電子研究所
In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of hash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N-it) and oxide trap charges (Q(ox)) under both channel-hot-electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N-it and Q(ox), Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay, and we found that the interface state generation iis the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read-disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes.
A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
(2002)
Chung, SS
;
Chen, SJ
;
Yang, CK
;
Cheng, SM
;
Lin, SH
For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has, been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.
A novel leakage current separation technique in a direct Tunneling regime gate oxide SONOS memory cell
(2003)
Chung, SS
;
Chiang, PY
;
Chou, G
;
Huang, CT
;
Chen, P
In this paper, data retention for various top and bottom oxide (tunnel oxide) SONOS cells has been extensively investigated. For the first time, a leakage current separation technique has been developed to distinguish the two leakage current components via thermionic and direct tunneling (DT) in the ONO layer. Results show that the short-term leakage is dominated by the direct tunneling, while the long-term leakage is dominated by the thermionic emission. The direct tunneling through either tunnel or blocking oxide can also be identified experimentally. These results are useful toward an understanding of the scaling of SONOS cell with focus on its reliabilities.
A numerical model for simulating MOSFET gate current degradation by considering the interface state generation
(1996)
Yih, CM
;
Chung, SS
;
Hsu, CCH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A physically-based built-in Spice Poly-Si TFT model for circuit simulation and reliability evaluation
(1996)
Chung, SS
;
Chen, DC
;
Cheng, CT
;
Yeh, CF
;
交大名義發表
A Poly-Si TFT model for circuit simulation in Spice is presented, combined with a device degradation model for the first time to evaluate the circuit reliability. Both I-V and C-V models for the whole device operating regime have been developed. In the I-V model, emphasis has been taken to derive the mobility degradation induced by the grain boundary potantial barrier height and trap density. The small geometry effect, off-state current and the parasitic BJT effect are also considered in the model. Good agreements between modeled and experimental data were achieved. To evaluate the circuit reliability after electrical stress, the device reliability model has also been developed. Finally, simulation a 27-stage ring oscillator has been demonstrated, which shows delay time of about 1 nsec per stage.
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
(1997-11-01)
Cheng, SM
;
Yih, CM
;
Yeh, JC
;
Kuo, SN
;
Chung, SS
A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N-it) and oxide charge (Q(ox)) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N-it and Q(ox) in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N-it and Q(ox) under various bias stress conditions, such as the hot-electron stress (I-G,I-max), I-B,I-max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N-it and Q(ox) has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, (EPROM)-P-2 cells since the above stress conditions, such as the I-G,I-max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively.
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
(1997-11-01)
Cheng, SM
;
Yih, CM
;
Yeh, JC
;
Kuo, SN
;
Chung, SS
A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N-it) and oxide charge (Q(ox)) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N-it and Q(ox) in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N-it and Q(ox) under various bias stress conditions, such as the hot-electron stress (I-G,I-max), I-B,I-max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N-it and Q(ox) has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, (EPROM)-P-2 cells since the above stress conditions, such as the I-G,I-max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively.
An accurate hot carrier reliability monitor for deep-submicron shallow S/D junction thin gate oxide n-MOSFET's
(1999)
Chung, SS
;
Chen, SJ
;
Yih, CM
;
Yang, WJ
;
Chao, TS
In this paper, an accurate criterion has been proposed for reliability evaluation of state-of-the-art deep-submicron S/D extension n-MOSFET's. A new monitor for HC reliability evaluation has been developed using total values of N-it in the effective channel length region, instead of commonly used substrate current(I-B), impact ionization rate (I-D/I-B), or peak/average N-it values. An accurate degradation model has thus been developed based on the N-it distribution and mobility scattering effect. Moreover, this approach has been successfully used to demonstrate the feasibility for gate-engineering studies.
An accurate RF CMOS gate resistance model compatible with HSPICE
(2004)
Lin, HW
;
Chung, SS
;
Wong, SC
;
Huang, GW
;
電子工程學系及電子研究所
Two important models, which are crucial to the RF CMOS, are the gate resistance and substrate resistance. Both are closely related to the development of accurate device and/or circuit models, such as noise. From the experimental observations, we found that the gate resistance depends largely on the bias and temperature. It will greatly impact the device performance at high frequency. For the first time, a simple and analytical physical-based gate resistance model is developed in this paper and has been implemented in Spice. The gate resistance is modeled by a parallel interconnection of the intrinsic gate resistance and a resistance coupled from the channel. The Spice simulation result of this model is more accurate than that of using a constant R-g model. A constant Rg model will overestimate the value of Y-11. While, in contrast, the proposed nonlinear gate resistance model with both bias and frequency dependent feature can achieve very good accuracy.
An efficient method for characterizing time-evolutional interface state and its correlation with the device degradation in LDD n-MOSFET's
(1996-06-01)
Lee, RGH
;
Wu, JP
;
Chung, SS
;
電子工程學系及電子研究所
;
電控工程研究所
A new characterization method is proposed to study the relationship between the hot-carrier-induced interface state N-it(x) and the device drain current degradation of submicron LDD n-MOSFET's. In this method, by making use of the conventional charge pumping measurement in combination with the power-lay dependence of interface damages on stress time, the spatial distribution N-it(x) and the effective damaged length L(dam) can be easily extracted. The time evolution of the interface state generation and its correlation with the device degradation can then be well explained. It is worthwhile to note that this newly-developed method requires no repetitive charge pumping measurements, and hence avoids he likely imposition of se-stress on tested devices. By combining the characterized L(dam) and N-it quantitatively, the results show that the damage at V-GS approximate to V-DS/2 is most highly localized among various stress biases, which can explain why the generated interface states will dominate the device drain current degradation at this bias after long-term operating conditions.
An improved interface characterization technique for a full-range profiling of oxide damage in ultra-thin gate oxide CMOS devices
(2003)
Chen, SJ
;
Lin, TC
;
Lo, DK
;
Yang, JJ
;
Chung, SS
In this paper, an improved gate-diode technique has been developed for the interface characterization on both n- and p-MOSFET's with gate oxide in the direct tunneling regime. This method has been demonstrated successfully for measuring oxide damage in all of the channel, space-charge (or junction), and drain extension regions in 20Angstrom ultra-thin gate oxide devices. As an application of the present method, the lateral profile of localized oxide damage due to Negative Bias Temperature Instability (NBTI) or Hot Carrier (HC) effect has been demonstrated. It provides us an understanding of the correlation between the device degradation and various stress-induced oxide damage in CMOS devices.
Characterization of hot-hole injection induced SILC and related disturbs in flash memories
(2001-02-01)
Yih, CM
;
Ho, ZH
;
Liang, MS
;
Chung, SS
;
電子工程學系及電子研究所
In this paper, we have proposed a new method for the study of disturb failure mechanisms caused by stress induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual components of SILC due to either carrier charging/disharging in the oxide or the positive charge/trap assisted electron tunneling into the floating gate, In addition, the present method is very sensitive with capability of measuring ultralow current (<10(-19) A), Results show that, at low oxide field, the disturb is mainly contributed by the so-called charging/disharging of carriers into/from the oxide due to the capacitance coupling effect. While at high oxide field, the positive charge/trap assisted electron tunneling induced floating-gate charge variation is the major cause of disturb failure.