Browsing by Author "Chung, SSS"

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Charge pumping profiling technique for the evaluation of plasma-charging-enhanced hot-carrier effect in short-N-channel metal-oxide-semiconductor field-effect transistors
(2002-07-01)
Chen, SJ
;
Chung, SSS
;
Lin, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Plasma etching of poly-silicon in a metal-oxide-semiconductor field-effect transistor (MOSFET) during the gate definition process induces edge damage at the gate-drain overlap edge. This edge damage will be further enhanced by the antenna effect and cause a more serious hot-carrier (HC) effect, particularly in short-channel devices. We call this phenomenon the plasma-charging-enhanced HC effect. In this paper, this plasma-charging-enhanced HC effect is evaluated by the charge pumping (CP) profiling technique, in which the enhanced damage at the gate-drain overlap gate oxide region can be identified. A three-phase plasma damage mechanism is then proposed to explain the observed effect. According to experimental results, it was shown that the interface traps generated at the gate-drain overlap edge are mainly attributed to the plasma-charging-enhanced HC effect. These interface traps (Nit) become the dominant mechanism of the drain current (ID) degradation, which increases with a reducing channel length (L). Again, the enhanced HC-effect-induced-degradation will dominate the device reliability under long-term operations.
Quantitative investigation of hot carrier induced drain current degradation in submicron drain-engineered metal-oxide-semiconductor field-effect-transistors
(2001-09-01)
Yang, JJ
;
Chung, SSS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Parameters, such as the total amount of hot carrier induced interface states and substrate current, are not sufficient to evaluate hot carrier reliability in drain-engineered metal-oxide-se mi conductor field-effect-transistors (MOSFETs). In this paper, for the first time, the distributions of hot carrier induced interface states are physically characterized and incorporated into two-dimensional device simulation to quantitatively study the structure-dependent drain current degradation in submicron MOSFETs, which give us insight into the relationship between degradation modes and device structures. The results show that the hot carrier induced series resistance effect in the sidewall spacer region plays an important role in drain-engineered MOSFETs. A different gate oxide thickness dependence of drain current degradation in thin gate oxide lightly-doped drain (LDD) MOSFETs is observed and is explained as the interface states enhanced series resistance effect in the LDD region.