Browsing by Author "Chung, Yueh-Ting"

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A Novel Random Telegraph Signal Method to Study Program/Erase Charge Lateral Spread and Retention Loss in a SONOS Flash Memory
(2011-03-01)
Ma, Huan-Chi
;
Chou, You-Liang
;
Chiu, Jung-Piao
;
Chung, Yueh-Ting
;
Lin, Tung-Yang
A novel random telegraph signal (RTS) method is proposed to characterize the lateral distribution of injected charge in program and erase states in a NOR-type silicon-oxide-nitride-oxide-silicon Flash memory. The concept of this method is to use RTS to extract an oxide trap position in the channel and then to use the trap and RTS as internal probe to detect a local channel potential change resulting from injected charge during program/erase. By using this method, the lateral width of the injected charge-induced channel potential barrier is shown to be around 20 nm in channel hot electron (CHE) program. Our method also confirms that Channel Initiated Secondary ELectron (CHISEL) program has a broader injected charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band tunneling erase holes is observed. Program-state V(t) retention loss models, charge vertical loss versus lateral migration, are reexamined by using this method. The polarity of a program-state charge distribution along the channel is explored within 10-20 program/erase cycles. Nitride charge vertical loss is verified by this method.
Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory
(2015-02-01)
Chung, Yueh-Ting
;
Su, Po-Cheng
;
Cheng, Yu-Hsuan
;
Wang, Tahui
;
Chen, Min-Cheng
A new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. This abrupt degradation is believed due to the creation of a new soft breakdown path in a switching dielectric by cycling stress. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. This cycling-induced degradation mode imposes a serious constraint on the number of SET-disturb pulses and thus an endurance cycle number in a resistive switching memory.
SET/RESET Cycling-Induced Trap Creation and SET-Disturb Failure Time Degradation in a Resistive-Switching Memory
(2016-06)
Chung, Yueh-Ting
;
Su, Po-Cheng
;
Lin, Wen-Jie
;
Chen, Min-Cheng
;
Wang, Tahui
Characterization and modeling of SET/RESET cycling-induced SET-disturb failure time degradation in a tungsten oxide resistive random access memory are performed. We find that write-disturb failure time in a high-resistance state (HRS) cell abruptly degrades by the orders of magnitude after certain SET/RESET cycles. To investigate this new degradation mode, we perform the constant voltage stress in high-resistance state (HRS) to characterize the trap generation in a switching dielectric by measuring a stress-induced leakage current and a low-frequency noise. The constant voltage stress is to emulate high-field stress and, thus, trap creation in SET/RESET cycling. We find that a low-field current in HRS by trap-assisted tunneling in a rupture region gradually increases in both the constant voltage stress and the SET/RESET cycling stress. The high-field stress-generated traps, unlike SET-induced oxygen vacancies, cannot be annihilated by RESET operation and are held responsible for a RESET endurance failure. A 3-D Monte Carlo model based on a percolation concept of oxide breakdown is developed to simulate a SET-disturb failure time. Our model includes both the stress-generated traps and the SET-disturb-induced oxygen vacancies. The model can well explain the observed abrupt and the drastic SET-disturb lifetime degradation, which is attributed to the formation of a conductive percolation path of stress-generated traps.
V-t Retention Distribution Tail in a Multitime-Program MLC SONOS Memory Due to a Random-Program-Charge-Induced Current-Path Percolation Effect
(2012-05-01)
Chung, Yueh-Ting
;
Huang, Tzu-I
;
Li, Chi-Wei
;
Chou, You-Liang
;
Chiu, Jung-Piao
A V-t retention distribution tail in a multitime-program (MTP) silicon-oxide-nitride-oxide-silicon (SONOS) memory is investigated. We characterize a single-program-charge-loss-induced Delta V-t in NOR-type SONOS multilevel cells (MLCs). Our measurement shows the following: 1) A single-charge-lossinduced Delta V-t exhibits an exponential distribution in magnitudes, which is attributed to a random-program-charge-induced current-path percolation effect, and 2) the standard deviation of the exponential distribution depends on the program-charge density and increases with a program V-t level in an MLC SONOS. In addition, we measure a V-t retention distribution in a 512-Mb MTP SONOS memory and observe a significant V-t retention tail. A numerical V-t retention distribution model including the percolation effect and a Poisson-distribution-based multiple-charge-loss model is developed. Our model agrees with the measured V-t retention distribution in a 512-Mb SONOS well. The observed V-t tail is realized mainly due to the percolation effect.