Browsing by Author "Deng, Chih-Kang"

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A simple Spacer technique to fabricate poly-Si TFTs with 50-nm nanowire channels
(2007-11-01)
Chang, Chia-Wen
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Deng, Chih-Kang
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Chang, Hong-Ren
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Chang, Che-Lun
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Lei, Tan-Fu
In this letter, polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 50-nm nanowire (NW) channels, which are fabricated without advanced photolithography by using a side-wall spacer-formation technique, are proposed for the first time. Because the polygate electrode is perpendicularly across poly-Si NW channels to form a trigatelike structure, the proposed poly-Si NW TFT owns outstanding gate controllability. In summary, a simple and low-cost scheme is proposed to fabricate high-performance poly-Si NW TFT suitable for future display manufacturing and practical applications.
CF4-plasma-induced fluorine passivation effects on poly-Si TFTs with high-kappa Pr2O3 gate dielectric
(2008)
Chang, Chia-Wen
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Huang, Po-Wei
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Deng, Chih-Kang
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Huang, Jiun-Jia
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Chang, Hong-Ren
High-performance polycrystalline silicon thin-film transistors (poly-Si TFTs) integrating high-kappa Pr2O3 gate dielectric and fluorine-passivated poly-Si film are demonstrated. High gate capacitance density and thin equivalent-oxide thickness provided by the high-kappa Pr2O3 gate dielectric have the advantage of increasing the driving current capability of the TFT device, but an undesirable off-state leakage current could be introduced from the high electric field near the drain side. Introducing fluorine atoms into poly-Si films by employing a low-temperature CF4 plasma treatment can effectively passivate the trap states. With 10 W CF4 plasma treatment on poly-Si film, the electrical characteristics of poly-Si Pr2O3 TFTs can be significantly improved, including a steeper subthreshold swing, smaller threshold voltage, higher field-effect mobility, and better on/off current ratio compared with that without CF4 plasma treatment. The maximum off-state leakage current of the fluorine-passivated TFT is more than one order of magnitude lower than that of the control TFT. Furthermore, the incorporation of fluorine atoms by CF4 plasma treatment also improves the reliability of poly-Si Pr2O3 TFTs against hot carrier stressing, which is due to the formation of stronger Si-F bonds in place of weak Si-H bonds in the poly-Si channel and at the Pr2O3 gate dielectric/poly-Si interface. Therefore, high-performance and high-reliability poly-Si TFTs with Pr2O3 gate dielectric and CF4 plasma treatment on poly-Si film are suitable for active-matrix liquid crystal display application. (c) 2007 The Electrochemical Society.
Characteristics of Pr2O3 gate dielectric thin-film transistors fabricated on fluorine-ion-implanted polysilicon films
(2007)
Chang, Chia-Wen
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Deng, Chih-Kang
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Huang, Jiun-Jia
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Chang, Hong-Ren
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Lei, Tan-Fu
A simple and effective scheme for fabricating high dielectric constant (high-kappa) praseodymium oxide (Pr2O3) gate dielectric thin-film transistors (Pr2O3 TFT) on fluorine-ion-implanted polysilicon films was proposed and demonstrated for the first time. Incorporating the fluorine-incorporation method with high-kappa Pr2O3 gate dielectric cannot only effectively passivate the trap states in the poly-Si film but also significantly increase the gate capacitance density. With the incorporation of fluorine ions, the electrical characteristics of Pr2O3 TFT can be remarkably improved, including smaller threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower gate-induced drain leakage current, and better on/off current ratio. In addition, the incorporation of fluorine ions in the poly-Si film also improves the reliability of Pr2O3 TFT against hot-carrier stress, which is attributed to the formation of stronger Si-F bonds. Therefore, the proposed scheme is a promising technology for high-performance solid-phase crystallized poly-Si TFTs. (c) 2007 The Electrochemical Society. All rights reserved.
Characterizing fluorine-ion implant effects on poly-Si thin-film transistors with Pr2O3 gate dielectric
(2008-06-01)
Chang, Chia-Wen
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Deng, Chih-Kang
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Wu, Shih-Chieh
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Huang, Jiun-Jia
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Chang, Hong-Ren
The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k. Pr2O3 as gate dielectric is investigated for the first time. Using the Pr2O3 gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr2O3/poly-Si interface to improve the device electrical properties. The Pr2O3 TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr2O3 TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr2O3 TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr2O3 TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.
Effects of CF(4) Plasma Treatment on the Electrical Characteristics of Poly-Silicon TFTs Using a Tb(2)O(3) Gate Dielectric
(2010-07-01)
Pan, Tung-Ming
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Li, Zhi-Hong
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Deng, Chih-Kang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we developed high-k Tb(2)O(3) poly-Si thin-film transistors (TFTs) using different CF(4) plasma power treatments. The high-k Tb(2)O(3) poly-Si TFT device with a 20-W plasma power exhibited better electrical characteristics in terms of a highly effective carrier mobility, a high-driving current, a low-threshold voltage, a small subthreshold slope, and a high I(ON)/I(OFF) current ratio. This result is attributed to the incorporation of fluorine atoms into the Tb(2)O(3)/poly-Si interface to reduce the trap-state density. The high-k Tb(2)O(3) poly-Si TFT prepared under a 20-W CF(4) plasma power also enhanced electrical reliabilities, including hot carrier and positive bias temperature instability. All of these results suggest that the CF(4) plasma-treated poly-Si Tb(2)O(3) TFT is a good candidate for high-performance low-temperature poly-Si TFTs.
Effects of CF4 Plasma Treatment on the Electrical Characteristics of Poly-Silicon TFTs Using a Tb2O3 Gate Dielectric
(2010-07-01)
Pan, Tung-Ming
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Li, Zhi-Hong
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Deng, Chih-Kang
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we developed high-k Tb2O3 poly-Si thin-film transistors (TFTs) using different CF4 plasma power treatments. The high-k Tb2O3 poly-Si TFT device with a 20-W plasma power exhibited better electrical characteristics in terms of a highly effective carrier mobility, a high-driving current, a low-threshold voltage, a small subthreshold slope, and a high I-ON/I-OFF current ratio. This result is attributed to the incorporation of fluorine atoms into the Tb2O3/poly-Si interface to reduce the trap-state density. The high-k Tb2O3 poly-Si TFT prepared under a 20-W CF4 plasma power also enhanced electrical reliabilities, including hot carrier and positive bias temperature instability. All of these results suggest that the CF4 plasma-treated poly-Si Tb2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.
Electrical enhancement of polycrystalline silicon thin-film transistors using fluorinated silicate glass passivation layer
(2008-02-01)
Chang, Chia-Wen
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Deng, Chih-Kang
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Huang, Jiun-Jia
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Wang, Tong-Yi
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Lei, Tan-Fu
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with a fluorinated silicate glass (FSG) passivation layer are proposed and demonstrated in this study. Experimental results reveal that the electrical characteristics can be improved by the incorporation of appropriate amounts of fluorine in the poly-Si film. The poly-Si TFTs with a FSG passivation layer show a high on-current, a low off-state gate-induced drain leakage (GIDL) current, a high field-effect mobility, and a suppressed kink effect, compared with the poly-Si TFTs with an undoped SiO(2) passivation layer. The presence of incorporated fluorine atoms from the FSG passivation layer in the poly-Si channel film can passivate the trap states at the grain boundaries. Furthermore, the incorporation of fluorine atoms can form stronger Si-F bonds near the source and drain sides to enhance the immunity against hot-carrier stress. In addition, the proposed poly-Si TFTs are easy to fabricate, have a low production cost, and are realized using a process compatible with modern TFT manufacturing technology.
Electrical properties of high-kappa praseodymium oxide polycrystalline silicon thin-film transistors with nitrogen implantation
(2008-02-01)
Deng, Chih-Kang
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Chang, Hong-Ren
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Chiou, Bi-Shiou
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper demonstrates the polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with high-kappa praseodymium oxide (Pr(2)O(3)) gate dielectric and nitrogen implantation to achieve high-performance characteristics for the first time. Nitrogen atoms with various dosages are implanted into amorphous silicon (alpha-Si) film to passivate the grain boundary trap states during solid-phase crystallization (SPC) annealing. From experimental results, the electrical characteristics of the Pr(2)O(3) poly-Si TFT implanted with the nitrogen dosage of 5 x 10(12) cm(-2) could be greatly improved. In addition, a better hot-harrier immunity of high-kappa Pr(2)O(3) poly-Si TFT could be also obtained.
Enhanced performance and reliability for solid-phase crystallized poly-Si TFTs with argon ion implantation (vol 154, pg J375, 2007)
(2008)
Chang, Chia-Wen
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Deng, Chih-Kang
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Chang, Che-Lun
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Lei, Tan-Fu
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電子工程學系及電子研究所
ESD robustness of thin-film devices with different layout structures in LTPS technology
(2006-12-01)
Deng, Chih-Kang
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Ker, Ming-Dou
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The electrostatic discharge (ESD) robustness of different thin-film devices, including three diodes and two thin-film transistors (TFTs) in low-temperature polysilicon (LTPS) technology, is investigated. By using the transmission line pulse generator (TLPG), the high-current characteristics and the secondary breakdown current (It2) of these thin-film devices are observed. The experimental results with different parameters and layout structures of these LTPS thin-film devices have been evaluated for optimizing ESD protection design for liquid crystal display (LCD) panel. (c) 2006 Elsevier Ltd. All rights reserved.
High-performance nanowire TFTs with metal-induced lateral crystallized poly-Si channels
(2008-05-01)
Chang, Chia-Wen
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Chen, Szu-Fen
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Chang, Che-Lun
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Deng, Chih-Kang
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Huang, Jiun-Jia
High-performance poly-Si thin-film transistors (TFTs) with 50-nm nanowire (NW) channels fabricated by integrating a simple spacer formation scheme and metal-induced-lateral-crystallization (MILC) technique are proposed. By using the sidewall spacer formation scheme, the NW channels with nanometer-scale feature sizes can be easily fabricated, exhibiting superior channel controllability through the triple-gate structure. In employing the MILC technique, the grain crystallinity of NW channels is significantly superior to that formed by the solid-phase-crystallization (SPC) technique. Therefore, the MILC NW TFT exhibits greatly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, and higher field-effect mobility, as compared to those of the SPC NW TFT. Moreover, the superior threshold-voltage rolloff characteristics of MILC NW TFT are also demonstrated.
High-performance solid-phase crystallized polycrystalline silicon thin-film transistors with floating-channel structure
(2008-04-01)
Chang, Chia-Wen
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Deng, Chih-Kang
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Chang, Che-Lun
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Liao, Ta-Chuan
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Lei, Tan-Fu
High-performance solid-phase crystallized polycrystalline silicon thin-film transistors with a floating-channel active region (FC poly-Si TFTs) are proposed in this study. A high-quality poly-Si channel film accompanied by a larger grain size and fewer microstructural defects could be obtained. Compared with the conventional poly-Si TFTs (CN poly-Si TFTs), the fabricated FC poly-Si TFTs exhibit superior electrical characteristics, including lower threshold voltage, higher field-effect mobility, and lower trap state density. These electrical performance improvements could be attributed to the fact that the a-Si film with a floating-channel structure can relieve the stress generated from the crystallization process accompanying the trap state density reduction and grain size enhancement. In addition, the FC poly-Si TFTs also exhibit improved hot-carrier stress immunity due to the reduced weak Si-H bonds from fewer grain boundaries in the poly-Si channel. Therefore, the proposed FC poly-Si TFTs can be easily fabricated by conventional solid-phase crystallization, and suitable for future high-performance flat-panel display applications.
On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process
(2007)
Ker, Ming-Dou
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Chuang, Jie-Yao
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Deng, Chih-Kang
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Kuo, Chung-Hong
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Li, Chun-Huai
The electrostatic discharge (ESD) robustness of diode-connected n-type thin-film transistors (N-TFTs) and diode-connected p-type thin-film transistors (P-TFTs) with different layout structures in a given low-temperature polycrystalline silicon (LTPS) process is investigated. By using the wafer-level transmission line pulsing (TLP) system, the high-current transient characteristics and the secondary breakdown current (It2) levels of the diode-connected TFTs under different device parameters and layout structures are directly measured on the glass substrate. Finally, one set of design rules for on-panel ESD protection design is suggested.
On-Panel Output Buffer With Offset Compensation Technique for Data Driver in LTPS Technology
(2006-06-01)
Ker, Ming-Dou
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Deng, Chih-Kang
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Huang, Ju-Lin
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電機學院
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College of Electrical and Computer Engineering
To overcome the offset voltage (V(OS)) of output buffer due to large variation on characteristics of thin-film transistor (TFT) in low-temperature polysilicon (LTPS) technology, a class-B output buffer with offset compensation circuit for the data driver is presented in this paper. This proposed class-B output buffer can operate at 50-kHz operation frequency with a 2-8-V output swing for extended graphic array (XGA) application, and it has been demonstrated in 3-mu m LTPS technology. Using the offset compensation technique, the V(OS) of output buffer can be controlled within +/- 100 mV under 2-to-8 V signal operation to achieve a high resolution and quality liquid crystal display (LCD) panel.
Stability of La(2)O(3) Metal-Insulator-Metal Capacitors under Constant Voltage Stress
(2010-01-01)
Wu, Shu-Hua
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Deng, Chih-Kang
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Hou, Tuo-Hung
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Chiou, Bi-Shiou
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電子工程學系及電子研究所
In this study, we demonstrate the stability of high-kappa La(2)O(3) metal-insulator-metal (MIM) capacitors under constant voltage stress (CVS). It was found that the variation in capacitance caused by CVS strongly depends on the injected charges regardless of stress biases. Furthermore, the quadratic voltage coefficient of capacitance (alpha) decreases with a logarithmic increase in dielectric loss. Charge trapping contributes to the relative capacitance variation under CVS while the reduced carrier mobility due to the stress-induced traps is responsible for the reduction of alpha. Additionally, high stability of 10-year lifetime is achieved for a 10-nm La(2)O(3) MIM capacitor with an 11.4 fF/mu m(2) capacitance density. (C) 2010 The Japan Society of Applied Physics
Stability of La2O3 Metal-Insulator-Metal Capacitors under Constant Voltage Stress
(2010-01-01)
Wu, Shu-Hua
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Deng, Chih-Kang
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Hou, Tuo-Hung
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Chiou, Bi-Shiou
;
電子工程學系及電子研究所
In this study, we demonstrate the stability of high-kappa La2O3 metal-insulator-metal (MIM) capacitors under constant voltage stress (CVS). It was found that the variation in capacitance caused by CVS strongly depends on the injected charges regardless of stress biases. Furthermore, the quadratic voltage coefficient of capacitance (alpha) decreases with a logarithmic increase in dielectric loss. Charge trapping contributes to the relative capacitance variation under CVS while the reduced carrier mobility due to the stress-induced traps is responsible for the reduction of alpha. Additionally, high stability of 10-year lifetime is achieved for a 10-nm La2O3 MIM capacitor with an 11.4 fF/mu m(2) capacitance density. (C) 2010 The Japan Society of Applied Physics