Browsing by Author "Diaz, CH"

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Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devices
(2002-01-01)
Wang, HCH
;
Wang, CC
;
Diaz, CH
;
Liew, BK
;
Sun, JYC
Optimization of a LDD doping profile to enhance hot carrier resistance in 3.3 V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFET's with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced as compared to the one without TED. The reason is that the TED effect can yield a more graded n(-) LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional (2-D) device simulation for electric field
Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology
(2000-12-01)
Wang, HCH
;
Diaz, CH
;
Liew, BK
;
Sun, JYC
;
Wang, TH
This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors, Arsenic/phosphorus LDI) nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated, Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n(-) LDD doping profile by taking advantage of phosphorus TED.
Interface induced uphill diffusion of boron: An effective approach for ultrashallow junction
(2001-02-01)
Wang, HCH
;
Wang, CC
;
Chang, CS
;
Wang, TH
;
Griffin, PB
This paper investigates anomalous diffusion behavior for ultra low energy implants in the extension or tip of PMOS devices. Transient enhanced diffusion (TED) is minimal at these low energies, since excess interstitials are very close to the surface, Instead, interface induced uphill diffusion is found, for the first time, to dominate during low temperature thermal cycles. The interface pile-up dynamics can be taken advantage of to produce shallower junctions and improve short channel effect control in PMOS devices, Attempts to minimize TED before spacer deposition by inclusion of extra RTA. anneals are shown to be detrimental to forming boron ultra shallow junctions.
Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs
(2005-01-01)
Sheu, YM
;
Yang, SJ
;
Wang, CC
;
Chang, CS
;
Huang, LP
The effect of shallow trench isolation mechanical stress on MOSFET dopant diffusion has become significant, and affects device behavior for sub-100-nm technologies. This paper presents a stress-dependent dopant diffusion model and demonstrates its capability to reflect experimental results for a state-of-the-art logic CMOS technology. The proposed stress-dependent dopant diffusion model is shown to successfully reproduce device characteristics covering a wide range of active area sizes, gate lengths, and device operating conditions.
Separation of channel backscattering coefficients in nanoscale MOSFETs
(2004-09-01)
Chen, MJ
;
Huang, HT
;
Chou, YC
;
Chen, RT
;
Tseng, YT
Channel backscattering coefficients in the kBT layer (near the source) of 1.65-nm-thick gate oxide, 68-nm gate length bulk n-channel MOSFETs are systematically separated into two distinct components: the quasithermal-equilibrium mean-free-path for backscattering and the width of the kBT layer. Evidence to confirm the validity of the separation procedure is further produced: 1) the near-source channel conduction-band profile; 2) the existing value of kBT layer width from the sophisticated device simulation; and 3) an analytic temperature-dependent drain current model for the channel backscattering coefficients. The findings are also consistent with each other and therefore corroborate channel backscattering as the origin of the coefficients. Other interpretations and clarifications are determined with respect to the very recently released Monte Carlo particle simulation. Consequently, it can be reasonably claimed that the separated components, as well as their dependencies on temperature and bias, are adequate while being used to describe the operation of the devices undertaken within the framework of the channel backscattering theory.
Temperature dependent channel backscattering coefficients in nanoscale MOSFETs
(2002)
Chen, MJ
;
Huang, HT
;
Huang, KC
;
Chen, PN
;
Chang, CS
The ratio of the mean-free-path to the critical length near the low-field source is key to channel backscattering characteristics in nanoFETs. To extract it, we perform temperature experiment from -40 degreesC to 75 degreesC on 17 Angstrom thick gate oxide MOSFETs with varying mask gate lengths down to 75 nm. In this paper we report that once the saturation drain current is measured against temperature, the mean-free-path lambda with respect to the critical length l can readily be assessed at pecific temperature. Dependencies on gate length, drain voltage, and gate voltage are then established that further enable nanoFETs scaling projections. The temperature dependent version of existing backscattering model is derived in this work.