Browsing by Author "Du, AY"

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A TaN-HfO2-Ge pMOSFET with novel SiH4 surface passivation
(2004-09-01)
Wu, N
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Zhang, QC
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Zhu, CX
;
Chan, DSH
;
Du, AY
In this letter, we demonstrate a novel surface passivation process for HfO2 Ge pMOSFETs using SiH4 surface annealing prior to HfO2 deposition. By using SiH4 passivation, a uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the HfO2 Ge MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and a similar to 140% higher peak mobility than that of the device with surface nitridation.
Effect of surface NH3 anneal on the physical and electrical properties of HfO2 films on Ge substrate
(2004-05-10)
Wu, N
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Zhang, QC
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Zhu, CX
;
Yeo, CC
;
Whang, SJ
Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN as the metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before the HfO2 deposition could result in significant improvement in both gate leakage current and the equivalent oxide thickness (EOT). It was possible to achieve a capacitor with an EOT of 10.5 Angstrom and a leakage current of 5.02x10(-5) A/cm(2) at 1 V gate bias. X-ray photoelectron spectroscopy analysis indicates the formation of GeON during surface NH3 anneal. The presence of Ge was also detected within the HfO2 films. This may be due to Ge diffusion at the high temperature (similar to400 degreesC) used in the chemical-vapor deposition process. (C) 2004 American Institute of Physics.
Electrical characteristics and suppressed boron penetration behavior of thermally stable HfTaO gate dielectrics with polycrystalline-silicon gate
(2004-10-04)
Yu, XF
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Zhu, CX
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Li, MF
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Chin, A
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Du, AY
The thermal stability and electrical characteristics of HfTaO gate dielectric with polycrystalline-silicon gate have been investigated. The incorporation of Ta into HfO2 enhances the crystallization temperature of film dramatically. Transmission electron microscopy micrographs confirm that HfTaO with 43% Ta film remains amorphous even after activation annealing at 950 degreesC for 30 s, and the formation of low-kappa interfacial layer is observably reduced. The capacitance-voltage curve of metal-oxide-semiconductor capacitor using HfTaO gate dielectric fits well with simulated curve, indicating good interface property between HfTaO and substrate. In addition, the boron penetration behaviors of HfTaO films are sufficiently suppressed as manifested by the narrow flat-band voltage shift. The negligible flat-band voltage shift in HfTaO with 43% Ta film is observed and attributed to its amorphous structure after device fabrication. (C) 2004 American Institute of Physics.
Formation of dual-phase HfO2-HfxSi1-xO2 dielectric and its application in memory devices
(2005-07-01)
Wang, YQ
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Chen, JH
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Yoo, WJ
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Yeo, YC
;
Yeo, YC
In this paper, we studied the phase-separation phenomenon of Hf0.5Si0.5O2 film deposited on SiO2 or sandwiched by SiO2, by x-ray photoelectron spectroscopy and transmission electron microscopy. The Hf0.5Si0.5O2 film underwent phase separation to form a doublet-phase HfO2-HfxSi1-xO2 (x < 0.5) film, and was used as a trapping layer in a metal-blocking oxide-silicon nitride-tunnel oxide-silicon-type memory structure, where the dual-phase HfO2-HfxSi1-xO2 (DPHSO) film replaces the conventional silicon nitride (Si3N4) trapping layer. The charge storage properties of the DPHSO film were investigated and compared with HfO2 and Si3N4. It was found that for a given electric field applied to the tunnel oxide, the programming speed of memory devices using a DPHSO or HfO2 film as a trapping layer is faster than that using SiA. This indicates the higher electron-capture efficiency of the DPHSO and HfO2 films. In addition, the double-phase microstructure of the DPHSO film also provided better retention property than pure HfO2. (c) 2005 American Institute of Physics.
Germanium pMOSFETs with Schottky-barrier germanide S/D, high-kappa gate dielectric and metal gate
(2005-02-01)
Zhu, SY
;
Li, R
;
Lee, SJ
;
Li, MF
;
Du, AY
Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as similar to5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.
Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode
(2004-10-01)
Zhu, SY
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Yu, HY
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Chen, JD
;
Whang, SJ
;
Chen, JH
Both P- and N-channel MOSFET's with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420degreesC. PMOSFETs with PtSi S/D show excellent electrical performance of an I-on/I-off similar to 10(7)-10(8) and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have similar to3 orders of magnitude larger I-off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the I-on/I-off similar to 10(5) at low drain voltage. It can be attributed to the relatively higher barrier height (Phi(n)) of DySi2-x/n-Si than that of PtSi/p-Si (Phi(p)) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (similar to1nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed. (C) 2004 Published by Elsevier Ltd.
N-type Schottky barrier source/drain MOSFET using ytterbium silicide
(2004-08-01)
Zhu, SY
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Chen, JD
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Li, MF
;
Lee, SJ
;
Singh, J
Ytterbium silicide, for the first time, was used to form the Schottky barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, wich is highly preferred in the establishment of Schottky barrier S/D transistor (SSDT) technology, including the HfO2 gate dielectric, and HaN/TaN metal gate. The YbSi2-x, silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I-on/I-off ratio of similar to10(7) and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron barrier height and better film morphology of the YbSi2-x/Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.
Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode
(2004-05-01)
Zhu, SY
;
Yu, HY
;
Whang, SJ
;
Chen, JH
;
Shen, C
This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-kappa gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi source/drain (S/D), excellent electrical performance of I-on/I-off similar to 10(7) - 10(8) and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, I-on/I-off can reach similar to 10(5) at V-ds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-kappa dielectric and metal-gate materials to be used in the future generation CMOS technology.