Browsing by Author "Du, Pei-Ying"

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A Comprehensive Characterization Method for Lateral Profiling of Interface Traps and Trapped Charges in P-SONOS Cell Devices
(2017-03)
Guo, Jyh-Chyurn
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Du, Pei-Ying
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A comprehensive characterization method has been developed in this paper for reliable lateral profiling of the interface traps (Delta N-it), localized charges (Delta N-ot), and trapped holes (Delta N-hole) in P-SONOS cell devices. Charge pumping current (I-CP) measurement can be used to probe Delta N-it and Delta N-ot from the increase of maximum I-CP (I-CP,I- max) and the shift of I-CP curve along the base level voltage (V-b). When increasing the program and erase (P/E) cycles, the negative threshold voltage (V-T) shift at both program and erase states suggests the generation of Delta N-hole. The evolution of Delta N-it, Delta N-ot, and Delta N-hole during P/E cycling can consistently explain the nonmonotonic variations of gate induced drain leakage current (I-GIDL) and substrate current (I-SUB) as well as dramatic differences between the source and drain. The lateral migration of Delta N-ot caused by extending P/E cycles may lead to the failure of two-bit operation in SONOS cell devices. The larger V-T shift and subthreshold swing, smaller read current, and lower transconductance may degrade the endurance and retention of P-SONOS when applied in Flash memory.
A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance
(2015)
Lo, Roger
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Du, Pei-Ying
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Hsu, Tzu-Hsuan
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Wu, Chen-Jun
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Guo, Jung-Yi
Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.
A study of gate-sensing and channel-sensing (GSCS) transient analysis method - Part II: Study of the intra-nitride behaviors and reliability of SONOS-type devices
(2008-08-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Huang, Tiao-Yuan
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Hsieh, Kuang-Yeu
For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and channel-sensing (GSCS) method. Our results clearly indicate that for electron injection (+FN program), the electron centroid migrates from the bottom toward the nitride center, whereas for hole injection (-FN erase), holes first recombine with the bottom electrons and then gradually move upward. For the electron de-trapping processes under -V(G) stressing, the trapped electrons de-trap first from the bottom portion of nitride. We also develop a method to distinguish the electron de-trapping and hole injection erasing methods by comparing the erasing current density (J) versus the bottom oxide electric field (E). At short-term high-temperature baking, the electrons move from the top portion toward the bottom portion, and this intra-nitride transport becomes more significant for a thicker nitride. On the other hand, after long-term baking, the charge loss mainly comes from the bottom portion of nitride.
P-channel SONOS transient current modeling for program and erase
(2006)
Du, Pei-Ying
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Guo, Jyh-Chyurn
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Lee, H. M.
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Chen, H. M.
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Shen, Rick
Transient current models with time and field dependence are proposed. The time dependence follows asymptotic t(-1) behavior with slower tunneling rate for erase (ERS) than program (PGM). The field dependence follows FN tunneling in higher field for PGM and intermediate field for ERS with relatively higher corner field for saturation. The models have been justified for P-channel SONOS (P-SONOS) with splits of ONO scheme.
Pulse-IV Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide
(2009-04-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Huang, Tiaci-Yuan
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Hsieh, Kuang-Yeu
The transient behavior of SONOS-type devices was investigated for the first time using pulse-IV technique. Three kinds of SONOS devices are studied: SONS (without top oxide), SONoS (with a thin top oxide), and SoNOS (with a thin bottom oxide). Devices with or without a thin tunnel oxide were able to provide very fast charge injection/detrapping, but their charge-transient behavior cannot be accurately monitored by conventional DC-IV method. By using specific pulse-IV setup for memory, we can measure the drain current response immediately after programming and erasing, as well as the fast charge relaxation under various reliability tests. The program and erase transient behavior shows that all devices are easily programmed and erased within 1 mu s at low gate voltages (< 6 V). Moreover, SONS shows the fastest program and erase speeds because of the absence of tunnel oxide, and silicon nitride has very low barrier height that offers fast injection. We have also examined the charge relaxation under various field and temperature conditions and found that the charge loss mainly came from external charge injection during retention, not from detrapping through thermionic emission.
STUDY OF GATE-INJECTION OPERATED SONOS-TYPE DEVICES USING THE GATE-SENSING AND CHANNEL-SENSING (GSCS) METHOD
(2009)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Huang, Tiao-Yuan
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Hsieh, Kuang-Yeu
SONOS devices using gate injection programming and erasing have better cycling endurance because the gate oxide is not stressed by PIE operations. This work studies the gate injection behavior in detail using the recently developed gate-sensing and channel-sensing (GSCS) technique. GSCS accurately locates the charge centroid during programming/erasing and reliability tests. For the first time, we can track the charge centroid for gate-injection "top BE-SONOS" and various SONOS-type devices. Our results indicate that the charge centroid after electron gate injection is close to the nitride center, irrespective of various nitride thickness and top dielectric. Moreover, there is electron and hole vertical mismatch after hole gate injection. Comparing the results from SONS, we can clearly prove that electrons are mainly distributed inside the bulk nitride instead of the interfaces between oxide and nitride. For SNOS and SNS, where there is electron and hole injection simultaneously, two-region approximation can give us more detailed information about electron and hole capture. By comparing experimental data with theoretical modeling, we have shown that nitride 7nm or thicker captures all the injected electrons up to total charge area density similar to 10(13)cm(-2).
Study of the gate-sensing and channel-sensing transient analysis method for monitoring the charge vertical location of SONOS-type devices
(2007-09-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Lai, Erh-Kun
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Huang, Tiao-Yuan
The gate-sensing and channel-sensing transient analysis method is studied in detail. This method introduces an additional gate-sensing capacitor to be compared with the conventional channel-sensing one. Sensing in both modes provides two equations that are suitable to solve for two variables-the charge density (Q) and the average charge vertical location (x). In this paper, the principle of this method is discussed in detail. Several factors that affect the measurement accuracy are also analyzed. The power of this method is demonstrated by program/erase cycling and data retention tests. This method is indeed a powerful tool for detailed understanding of trapping dynamics.
Study of Thyristor-Mode Dual-Channel NAND Flash Devices
(2018-01-01)
Lo, Roger
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Lue, Hang-Ting
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Chen, Weichen
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Du, Pei-Ying
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Hsu, Tzu-Hsuan
A novel dual-channel 3D NAND device was proposed previously [1]. In addition to the N- and P-channel read operations, such device can also perform a special "thyristor mode" which possesses super steep subthreshold slope (S.S. similar to 0). In this work, we studied 4 different types of read methods with the same device, which are normal N- and P-channel read, and thyristor-mode N- and P-channel read, respectively. These 4 different read methods can be carried out by just simply changing the bias arrangements of wordlines so that the IdVg curves can behave differently. An interesting finding is that the Vt window of PIE cycling and retention are quite different among these sensing methods. It may provide a new methodology to understand the charge storage mechanisms. 'this work provides a comprehensive study for understanding the operation physics of this novel device.