Browsing by Author "Feng, Chih-Wei"

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A Reliable Brain Computer Interface Implemented on an FPGA for a Mobile Dialing System
(2014-01-01)
Feng, Chih-Wei
;
Hu, Ting-Kuei
;
Chang, Jui-Chung
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six frequency bands (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose a phone number by gazing at the display interface. This proposed EEG system has been implemented in Field-Programmable Gate Arrays (FPGA), and shows high accuracy, high integration density, and low cost. These features are meaningful for implementing a real-time SSVEP-based BCI.
A Reliable Brain Computer Interface Implemented On FPGA For Mobile Dialing System
(2015)
Feng, Chih-Wei
;
Chang, Jui-Chung
;
Chen, Wei-Chen
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six buttons (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose the number by gazing at the computer interface. This proposed EEG (Electroencephalography) system has been implemented in Field-Programmable Gate Arrays (FPGA) and it features high accuracy, integration density, and low cost. These features are meaningful for implementing a real time SSVEP-based BCI.
An Efficient VLSI Implementation of SVD Processor of On-line Recursive ICA for Real-time EEG System
(2014-01-01)
Fang, Wai-Chi
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Chang, Jui-Chung
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Huang, Kuan-Ju
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Feng, Chih-Wei
;
Chou, Chia-Ching
This paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the critical computational latency is associated with the SVD process. Accordingly, the performance of the SVD processor should be prioritized. Going beyond previous research [1], this work presents a novel design of coordinate rotation digital computer (CORDIC) engine which is optimized and speeded up to avoid structural hazards. Finally, the processor is fabricated using TSMC 40nm CMOS technology in a 16-channel EEG system. The computation time of the SVD processor is reduced by 24.7% and the average correlation coefficient between original source signals and extracted ORICA signals is 0.95452.
Development of a Reliable SSVEP-Based BCI Mobile Dialing System
(2016)
Chen, Tsan-Yu
;
Feng, Chih-Wei
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and the automatic artifacts removal system based on BSS-CCA method and Steady-State Visual Evoked Potential (SSVEP). Through six frequency bands (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose a phone number by gazing at the display interface. Implementing a prototype of the SSVEP-based BCI system verifies the effectiveness of the proposed system. Experimental results show that the subjects\' SSVEP can successfully control the dial device through the proposed BCI system with high identification accuracy.