Browsing by Author "HWANG, JS"

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AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES
(1985)
WU, CY
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HWANG, JS
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CHANG, C
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CHANG, CC
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電控工程研究所
EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS
(1991-05-01)
HWANG, JS
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WU, CY
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交大名義發表
;
電子工程學系及電子研究所
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National Chiao Tung University
Two techniques are proposed which enhance the optimisation efficiency of CMOS combinational logic circuits. One uses transition times (rise and fall times) of each gate as variables of the optimisation process. The other technique uses the optimal characteristic waveform synthesising method (OCWSM) to obtain the initial guess for the optimisation process. The optimisation process, with these two techniques, can perform sizing and optimisation for circuits with a smaller fixed-delay specification than other sizing and optimisation algorithms. The circuits sized using the proposed algorithm have shown a smaller power dissipation, especially when the delay specification is small. The CPU time consumed is reasonable. High-speed low-power circuits are thus more realisable using the proposed algorithm.
NEW FAST FIXED-DELAY SIZING ALGORITHM FOR HIGH-PERFORMANCE CMOS COMBINATIONAL LOGIC-CIRCUITS AND ITS APPLICATIONS
(1992-09-01)
HWANG, JS
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WU, CY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A sizing methodology called the near-characteristic waveform-synthesising method (NCWSM) is proposed to determine the device sizes of CMOS combinational logic circuits under a fixed delay specification. By using accurate physical timing models and the NCWSM, a fixed-delay sizing algorithm is developed and implemented, which sizes circuits quickly and globally. It can handle CMOS inverters, multi-input NAND/NOR gates, and AOI/OAI gates, all with device channel lengths down to 1.5 mum. It is shown through experimental verifications that the proposed algorithm can size a circuit with much smaller CPU time than that for the heuristic approach, and the resultant circuit power dissipations are nearly the same. As the circuit complexity increases, the above advantageous feature becomes more significant and the minimum realisable delay is even smaller than that of the heuristic approach. With high efficiency and delay accuracy, the proposed sizing algorithm and methodology can handle large-scale circuits with less design time. It can also serve to provide a good initial guess for more advanced sizing operations.
PHYSICAL TIMING MODELS OF SMALL-GEOMETRY CMOS INVERTERS AND MULTI-INPUT NAND NOR GATES AND THEIR APPLICATIONS
(1989-06-01)
WU, CY
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HWANG, JS
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電子工程學系及電子研究所
;
電控工程研究所
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Department of Electronics Engineering and Institute of Electronics
TIMING MACROMODELS FOR CMOS STATIC SET RESET LATCHES AND THEIR APPLICATIONS
(1988-05-01)
WU, CY
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LI, C
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HWANG, JS
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交大名義發表
;
電子工程學系及電子研究所