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學術出版;;Publications
期刊論文;;Articles
AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES
AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES
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A1985AUB1500033.pdf
(2.11 MB)
Date
1985
Authors
WU, CY
HWANG, JS
CHANG, C
CHANG, CC
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https://ir.lib.nycu.edu.tw/handle/11536/4823
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