Browsing by Author "Han, Ming-Hung"

Now showing 1 - 20 of 23

3D 65nm CMOS with 320 degrees C Microwave Dopant Activation
(2009)
Lee, Yao-Jen
;
Lu, Yu-Lun
;
Hsueh, Fu-Kuo
;
Huang, Kuo-Chin
;
Wan, Chia-Chen
For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is. demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P-31 for n-MOS TFTs at a low temperature of 320 degrees C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
3D Device Simulation of Work Function and Interface Trap Fluctuations on High-kappa/Metal Gate Devices
(2010)
Cheng, Hui-Wen
;
Li, Fu-Hai
;
Han, Ming-Hung
;
Yiu, Chun-Yen
;
Yu, Chia-Hui
This work, for the first time, examines the work function fluctuation (WKF) and interface trap fluctuation (ITF) using experimentally calibrated 3D device simulation on high-kappa / metal gate technology. The random WKs result in 36.7 mV threshold voltage fluctuation (sigma V(th)) for 16 nm N-MOSFETs with TiN gate, which is rather different from the result of averaged WKF (AWKF) method [1] due to localized random WK effect. The ITF affects the subthreshold region (the normalized sigma I(D) > 48%) and is suppressed for devices under strong inversion. Estimation of statistical covariance confirms the dependence of IT on the metal gate's WK; thus, the impacts of WKF and ITF on device and circuit variability should be considered together properly. Such variability induced static noise margin fluctuation of SRAM exceeds the influence of random dopants and cannot be ignored.
A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage
(2012-04-01)
Han, Ming-Hung
;
Chen, Hung-Bin
;
Chang, Chia-Jung
;
Wu, Jia-Jiun
;
Chen, Wen-Chong
In this work, double reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device combines a new implant technology without using additional mask in standard 0.18 mu m technology has been proposed and successfully fabricated. The breakdown voltage (BV) can be improved significantly with simply changing the implanted region length in this implant technology. Firstly, hydrodynamic transport simulations which analyze the high bias condition electric field distributions are examined to predict and explain the increase of breakdown voltage. Then the fabricated devices process flow is demonstrated, the structures are performed, and the breakdown voltages increase with different n-type double diffusion (NDD) photoresistor (PR) size using the change of PR exposure dose are investigated. The measurement results show that maximum NDD PR size achieves BV improvement of 6.3%, and 5% increase of figure of merit (FOM) evaluation. Throughout the whole fabrication process, no additional mask and device area show the potential of cost effective with the proposed technique. Such devices with good off-state breakdown voltage and specific on-resistance are very competitive with similar technologies and show good promising in system on chip (SOC) applications. (C) 2012 The Japan Society of Applied Physics
Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis
(2013-02-01)
Han, Ming-Hung
;
Chang, Chun-Yen
;
Jhan, Yi-Ruei
;
Wu, Jia-Jiun
;
Chen, Hung-Bin
The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (V-th), on current (I-on), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.
Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel
(2013-07-01)
Chen, Hung-Bin
;
Chang, Chun-Yen
;
Lu, Nan-Heng
;
Wu, Jia-Jiun
;
Han, Ming-Hung
This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 10(8) because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.
Device and Circuit Performance Estimation of Junctionless Bulk FinFETs
(2013-06-01)
Han, Ming-Hung
;
Chang, Chun-Yen
;
Chen, Hung-Bin
;
Cheng, Ya-Chi
;
Wu, Yung-Chun
The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (V-th) roll-off characteristics at supply voltage (V-DD) 1 V. Analyses of electron density and electric field distributions in ON-state and OFF-state also show that the JL devices have better ON-OFF current ratios. Regarding design aspects, the effects of channel doping concentration (N-ch) and Fin height (H)/width (W) on device V-th are also compared. In addition, the V-th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (N-sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (t(HL)) and low-to-high delay time (t(LH)) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.
Discrete-Dopant-Induced Power-Delay Characteristic Fluctuation in 16 nm Complementary Metal-Oxide-Semiconductor with High Dielectric Constant Material
(2010)
Han, Ming-Hung
;
Li, Yiming
;
Hwang, Chih-Hong
;
傳播研究所
;
電機工程學系
In this work, we carry out an experimental validated three-dimensional "atomistic'' device-circuit coupled simulation to study the discrete-dopant-induced power and delay fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits. The equivalent gate oxide thicknesses (EOTs) of planar CMOS range from 1.2 nm to 0.2 nm. SiO(2) is used at gate oxide thicknesses of 1.2 and 0.8 nm, Al(2)O(3) at an EOT of 0.4 nm, and HfO(2) at an EOT of 0.2 nm. Under the same device threshold voltage, as EOT decreases from 1.2 to 0.2 nm, the fluctuations of threshold voltage and gate capacitance for CMOS transistors are reduced by 43 and 55%, respectively. For the state-of-art nanoscale circuits using high-dielectric constant (high-kappa) materials, the delay time fluctuation is suppressed significantly from 0.1 to 0.03 ps. For the power characteristics, although the nominal powers of circuits using high-kappa dielectrics are increased owing to the increased EOT, the fluctuations of dynamic power, short circuit power, and static power are reduced by 40, 70, and 30%, respectively. (C) 2010 The Japan Society of Applied Physics
Effect of Process Variation on 15-nm-Gate Stacked Multichannel Surrounding-Gate Field Effect Transistor
(2009)
Han, Ming-Hung
;
Cheng, Hui-Wen
;
Hwang, Chih-Hong
;
Li, Yiming
;
傳播研究所
Stacked multichannel transistor architectures were proposed recently which possess very attractive electrical characteristics on low leakage current and high driving current per layout area. However, due to complex manufacturing process, the process variation effect is inevitable and whose impact is unknown. Therefore, this study investigates the impact of process variation on 15-nm-gate stacked multichannel transistors consisting of the gate length deviation, channel position variation, quadruple-shaped channel structure and elliptic gate oxide. Our preliminary result shows that the stacked multichannel devices have good immunity to the gate length deviation and channel spacing variations; however, they are sensitive to the gate coverage ratio and gate oxide thickness variations. This study provides an insight into the device characteristic variations, which may benefit the development of nanoscale stacked multichannel transistors and circuits.
Effect of the Circle-Grid Electrodes on Concentrated GaAs Solar Cell Efficiency
(2014-09-01)
Chung, Chen-Chen
;
Binh Tinh Tran
;
Han, Ming-Hung
;
Lin, Kung-Liang
;
Yu, Hung-Wei
In this study, we investigate the effect of the shading factor of the front grid pattern on concentrated solar cell efficiency, taking the trade-off between the series resistance of the electrodes and the amount of incident light into consideration. We examine the thermal effect with regard to five different circle-grid electrode patterns of the front contact. The front contacts with different grid patterns affect the characteristics of light-concentrated-type GaAs single-junction solar cells. The device parameters analyzed include the open-circuit voltage (V-oc), short-circuit current (I-sc), fill factor (FF) and conversion efficiency (eta). The results of our study show that for a concentration ratio greater than 60x with AM1.5G, the device with a shading factor of 7.1% has the best cell efficiency of 27.05%, due to the smaller current crowding at the center spot. The results indicate that the conversion efficiency of solar cells can be improved by establishing a compromise between the shading effect and the series resistance effect.
High voltage characteristics of junctionless poly-silicon thin film transistors
(2013-09-16)
Cheng, Ya-Chi
;
Wu, Yung-Chun
;
Chen, Hung-Bin
;
Han, Ming-Hung
;
Lu, Nan-Heng
The breakdown voltage (V-BD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state V-BD of 53.4V is several times larger than V-BD of 9.5V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications. (C) 2013 AIP Publishing LLC.
Improving Breakdown Voltage of LDMOS Using a Novel Cost Effective Design
(2013-05-01)
Han, Ming-Hung
;
Chen, Hung-Bin
;
Chang, Chia-Jung
;
Tsai, Chi-Chong
;
Chang, Chun-Yen
A reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device with the concept of charge compensation using p-implant layer (PIL) without additional process step is proposed in standard 0.18-mu m technology. By simply using the p-type drift drain (PDD) implantation of p-type LDMOS into n-type LDMOS, breakdown voltage (VBD) is substantially improved. For a thorough study of device phenomena, hydrodynamic transport simulations are first performed to analyze the electric field distributions at high voltage bias in order to explain increases in breakdown voltage and predict its optimal design parameter. Then fabrication of the devices is performed and shows that the breakdown voltages increase significantly. The measurement results show a 12% improvement in VBD and a 5% improvement in figure of merit (FOM). Throughout the fabrication process, the enlarged breakdown voltage obtained by the PIL without additional process and device area show the potential of cost effective. Because such devices have good off-state breakdown voltage and specific on-resistance, they are very competitive with similar technologies and promising system-on-chip (SOC) applications.
Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method
(2019-01-01)
Chen, Lun-Chun
;
Chen, Hung-Bin
;
Chang, Yu-Shuo
;
Lin, Shih-Han
;
Han, Ming-Hung
A low-voltage programmable gate-all-around (GAA) nanosheet poly-Si thin-film transistor (TFT) nonvolatile memory (NVM), which uses band-to-band tunneling induced hot electron (BBHE) programming, is demonstrated. The BBHE method is extremely efficient for programming data in the p-type GAA nanosheet TFT NVM because the GAA nanosheet structure enhances the source-to-drain component of the electric field in its channel. Therefore, the enhanced electric field of the BBHE phenomenon creates energetic electrons that surmount the tunneling oxide barrier easily and pass shallow traps in the charge trapping layer of the GAA TFT NVM. Consequently, the p-type GAA TFT NVM achieves low-voltage programming bias and satisfactory data retention.
Performance Comparison Between Bulk and SOI Junctionless Transistors
(2013-02-01)
Han, Ming-Hung
;
Chang, Chun-Yen
;
Chen, Hung-Bin
;
Wu, Jia-Jiun
;
Cheng, Ya-Chi
The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable ON/OFF current ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an ON/OFF current ratio of 10(5) at W = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage V-th of the JL bulk FinFET can be easily tuned by varying substrate doping concentration N-sub. The modulation range of V-th as N-sub changes from 10(18) to 10(19) cm(-3), which is around 30%.
Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies
(2010-02-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Han, Ming-Hung
;
傳播研究所
This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (sigma V(th)); however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the sigma V(th) and is therefore proportional to the trend of sigma V(th). The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.
Quantum hydrodynamic simulation of discrete-dopant fluctuated physical quantities in nanoscale FinFET
(2011-01-01)
Li, Yiming
;
Cheng, Hui-Wen
;
Han, Ming-Hung
;
傳播研究所
;
電機工程學系
Impact of the discrete dopants on device performance is crucial in determining the behavior of nanoscale semiconductor devices Atomistic quantum mechanical device simulation for studying the effect of discrete dopants on device s physical quantities is urgent This work explores the physics of discrete-dopant-induced characteristic fluctuations in 16-nm fin-typed field effect transistor (FinFET) devices Discrete dopants are statistically positioned in the three-dimensional channel region to examine associated carrier's characteristic concurrently capturing "dopant concentration variation" and "dopant position fluctuation" An experimentally validated quantum hydrodynamic device simulation was conducted to investigate the potential profile and threshold voltage fluctuations of the 16-nm FinFET Results of this study provide further insight into the problem of fluctuation and the mechanism of immunity against fluctuation in 16-nm devices (C) 2010 Elsevier BV All rights reserved
Simulation of characteristic variation in 16 nm gate FinFET devices due to intrinsic parameter fluctuations
(2010-03-05)
Li, Yiming
;
Hwang, Chih-Hong
;
Han, Ming-Hung
;
傳播研究所
;
電機工程學系
High-kappa/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively explores the physics and mechanism of the intrinsic parameter fluctuations in nanoscale fin-type field-effect transistors by using an experimentally validated three-dimensional quantum-corrected device simulation. The dominance fluctuation sources in threshold voltage, gate capacitance and cutoff frequency have been found. The emerging fluctuation source, workfunction fluctuation, shows significant impacts on DC characteristics; however, its impact is reduced in AC characteristics due to the screening effect of the inversion layer. Additionally, the channel discrete dopant may enhance the electric field and therefore make the averaged cutoff frequency of fluctuated devices larger than the nominal value of cutoff frequency.
Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits
(2009)
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Han, Ming-Hung
;
Lee, Kuo-Fu
;
Cheng, Hui-Wen
This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold voltage fluctuation; however, the WKF brings less impact on the gate capacitance due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the threshold voltage fluctuation, and therefore is proportional to the trend of threshold voltage fluctuation. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency, are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can in turn be used to optimize nanoscale MOSFET and circuits.
Statistical Simulation of Metal-Gate Work-function Fluctuation in High-kappa/Metal-Gate Devices
(2010)
Yu, Chia-Hui
;
Han, Ming-Hung
;
Cheng, Hui-Wen
;
Su, Zhong-Cheng
;
Li, Yiming
In this work, we statistically examine the emerging high-kappa / metal gate work-function fluctuation (WKF) induced threshold voltage (V(th)) fluctuations in 16-nm-gate MOSFET devices. Our Monte-Carlo model extensively evaluates the impact of WKF for different technology node, metal grain size, and gate material. This model provides us to identify suitable materials and fabrication processes that can significantly reduce the impact of Vth fluctuation owing to WKF. First, four kinds of gate material are examined and TiN possesses the smallest Vth fluctuation. For fabrication process, a fast deposition of metal at lower temperature prevents the metal grain not to grow to large size result in a smaller variation. In addition, an idea of modeling multilayer metal gate WKF is also presented and discussed, in which the first layer plays the most important role, compared with other layers, for the fluctuation suppression.
Statistical Simulation of Static Noise Margin Variability in Static Random Access Memory
(2010-11-01)
Li, Yiming
;
Cheng, Hui-Wen
;
Han, Ming-Hung
;
傳播研究所
;
電機工程學系
In this paper, we examine the impact of random-dopant-fluctuation (RDF), process-variation-effect (PVE), and workfunction-fluctuation (WKF), on 16-nm-gate metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) cells. For planar MOSFETs with a threshold voltage (V(th)) of 140mV, the nominal static noise margin (SNM) of six-transistor (6T)-SRAM with unitary cell ratio (CR) is only 20mV; and the normalized SNM fluctuations (SNM) induced by RDF, PVE, and WKF are 80%, 31%, and 48%, respectively, which may damage SRAM's operation. Two improvement approaches are further implemented; first, eight-transistor (8T)-SRAM and 6T-SRAM with increased CR are examined. Compared with the conventional 6T-SRAM, under the same Vth, the SNM of 8T-SRAM is enlarged to 233 mV and the corresponding RDF, PVE, and WKF-induced SNM are reduced to 9.5%, 6.4%, and 7%, respectively, at a cost of 30% extra chip area. Without increasing chip area, device with raised Vth, doping profile engineering and using silicon-on-insulator fin-type field-effect transistors (SOI FinFETs) are further advanced. The 6T SOI FinFETs SRAM exhibits the smallest sigma SNM, with merely 5.3%, 1.2%, and 2.3%, resulting from RDF, PVE, and WKF, respectively, where the value of SNM is equal to 125 mV.
Statistical variability in FinFET devices with intrinsic parameter fluctuations
(2010-05-01)
Hwang, Chih-Hong
;
Li, Yiming
;
Han, Ming-Hung
;
傳播研究所
;
電機工程學系
High-kappa/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively estimates the influences of the intrinsic parameter fluctuations on nanoscale fin-type field-effect-transistors and circuits by using an experimentally validated three-dimensional device and coupled device-circuit simulations. The dominance fluctuation source in threshold voltage, gate capacitance, cut-off frequency, delay time, and power has been found. The emerging fluctuation source, workfunction fluctuation, shows significant impacts on DC characteristics: however, can be ignored in AC characteristics due to the screening effect of the inversion layer. (C) 2010 Elsevier Ltd. All rights reserved.