Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

Abstract

The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (V-th) roll-off characteristics at supply voltage (V-DD) 1 V. Analyses of electron density and electric field distributions in ON-state and OFF-state also show that the JL devices have better ON-OFF current ratios. Regarding design aspects, the effects of channel doping concentration (N-ch) and Fin height (H)/width (W) on device V-th are also compared. In addition, the V-th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (N-sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (t(HL)) and low-to-high delay time (t(LH)) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.