Browsing by Author "Ho, Chang-An"

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92% High Efficiency and Low Current Mismatch Interleaving Power Factor Correction Controller With Variable Sampling Slope and Automatic Loading Detection Techniques
(2013-11-01)
Su, Yi-Ping
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Chen, Chun-Yen
;
Ni, Chia-Lung
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Kang, Yu-Chai
;
Chen, Yi-Ting
This paper proposes the dual nondeadtime variable sampling slope technique to carry out precise phase sensing and suppress phase error in interleaving power factor correction (PFC) controller over a whole ac switching cycle for low current mismatch. Furthermore, the proposed automatic loading detection (ALD) technique can keep efficiency higher than 92% over a wide load range due to accurately controlling the ON/OFF of dual phases. The test circuit fabricated in the TSMC 0.5-mu m 800-V UHV process shows that the highly integrated interleaving PFC can deliver a high power of 180 W and a high efficiency of 95% at an output power of 180 W.
A Single-Inductor Dual-Output Converter with Switchable Digital-or-Analog Low-Dropout Regulator for Ripple Suppression and High Efficiency Operation
(2012)
Lee, Yu-Huei
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Chen, Wei-Chung
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Chiu, Chao-Chang
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Peng, Shen-Yu
;
Chu, Kuan-Yu
a single-inductor dual-output (SIDO) converter with the switchable digital-or-analog (D/A) low-dropout (LDO) regulator achieves an analog dynamic voltage scaling (ADVS) function for ripple suppression and high efficiency in system-on-achip (SoC). The ADVS function helps dynamically adjust the dropout voltage of the switchable D/A LDO regulator with analog operation for ripple suppression according to the load current. On other hand, the switchable D/A LDO regulator activates the digital operation for high efficiency at light loads since the dropout voltage of the LDO regulator can be further reduced. Besides, the bidirectional asynchronous signal pipeline (BASP) can realize the 50nA quiescent current in digital LDO regulator. This chip was fabricated by the 40 nm CMOS process. Experimental results demonstrate the switchable LDO regulator operation with the peak efficiency of 92% and the 7 mV output voltage ripple at 200 mA load because of the ripple suppression. The efficiency can be kept higher than 83% even the load current is 1 mA.
Automatic Loading Detection (ALD) Technique for 92% High Efficiency Interleaving Power Factor Correction (PFC) Over a Wide Output Power of 180W
(2012)
Tsai, Jen-Chive
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Chen, Chun-Yen
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Chen, Yi-Ting
;
Ni, Chia-Lung
;
Su, Yi-Ping
the proposed automatic loading detection (ALD) technique keeps high efficiency in interleaving power factor correction (PFC) over a wide load range. With the advantages of small input/output filter and output ripple in the interleaving mechanism, the improved efficiency by the ALD technique at light loads due to reduced switching loss can be widely used in the adapter of portable electronics. The ALD technique can calculate the power by the detection of peak input voltage to reduce the switching loss since the slave channel can be completely turned off for power saving at light loads. Therefore, the boundary control mode (BCM) control can simultaneously provide high power and keep high conversion efficiency both at light and heavy loads. The highly integrated PFC controller fabricated in TSMC 800V UHV process shows high efficiency of 92% over a wide output power of 180 W.
Real-Time Instruction-Cycle-Based Dynamic Voltage Scaling (iDVS) Power Management for Low-Power Digital Signal Processor (DSP) with 53% Energy Savings
(2012)
Peng, Shen-Yu
;
Lee, Yu-Huei
;
Wu, Chun-Hsien
;
Huang, Tzu-Chi
;
Chen, Ke-Horng
this paper presents an instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for a low-power processor design. The iDVS technique is fully compatible with conventional DVS scheduler algorithms. Furthermore, an additional iDVS design flow embedded in the standard cell lib flow is proposed to implement the iDVS-based DSP. In addition, the fast-response bidirectional asynchronous wave-pipeline (BAWP) digital low-dropout (LDO) regulator is also presented to improve the iDVS performance. The iDVS-based DSP chip implemented in an HH-NEC 0.18 mu m standard CMOS process demonstrates 53% energy savings over that without the iDVS technique.