Browsing by Author "Ho, Chia-Tung"

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InTraSim: Incremental Transient Simulation of Power Grids
(2017-12-01)
Lee, Yu-Min
;
Ho, Chia-Tung
;
電機工程學系
;
Department of Electrical and Computer Engineering
Effective transient power grid simulators are needed during design processes because a designed power grid needs to be numerously analyzed. This paper builds an efficient and reliable incremental power grid transient simulator, which we name it InTraSim, by integrating macro modeling techniques, sparse recovery mechanisms, an innovated pseudo-node value estimation method, and an initiated adaptive error control scheme. InTraSim is able to deal with not only element-value alterations of designs but also topology modifications of designs.
Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs
(2013-01-01)
Wei, Shu-Han
;
Lee, Yu-Min
;
Ho, Chia-Tung
;
Sun, Chih-Ting
;
Cheng, Liang-Chia
This work presents effective techniques for minimizing wiring resources and power TSVs (PTSVs) of 3-D power delivery network design under IR drop constraints. First, a 3-D power grid topology optimization is performed to generate power grid by utilizing locally uniform and globally non-uniform power grid configurations. After that, two developed power TSV planners are executed to minimize the maximum IR drop without the full-chip power-grid analysis. Finally, the above procedures are repeatedly performed with a rescue procedure to remedy the violated constraints until the designed PDN is satisfied. To further enhance the design procedure, a partition-based design flow is proposed by dividing the entire chip into tiles, and each of them is designed independently by the proposed procedure. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of partition-based strategy in the design flow is imperative.
Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs
(2013)
Wei, Shu-Han
;
Lee, Yu-Min
;
Ho, Chia-Tung
;
Sun, Chih-Ting
;
Cheng, Liang-Chia
This work presents effective techniques for minimizing wiring resources and power TSVs (PTSVs) of 3-D power delivery network design under IR drop constraints. First, a 3-D power grid topology optimization is performed to generate power grid by utilizing locally uniform and globally non-uniform power grid configurations. After that, two developed power TSV planners are executed to minimize the maximum IR drop without the full-chip power-grid analysis. Finally, the above procedures are repeatedly performed with a rescue procedure to remedy the violated constraints until the designed PDN is satisfied. To further enhance the design procedure, a partition-based design flow is proposed by dividing the entire chip into tiles, and each of them is designed independently by the proposed procedure. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of partition-based strategy in the design flow is imperative.
ThermPL: Thermal-aware Placement Based on Thermal Contribution and Locality
(2016)
Song, Jinxing
;
Lee, Yu-Min
;
Ho, Chia-Tung
;
電機工程學系
;
Department of Electrical and Computer Engineering
This work builds a thermal-aware placer, ThermPL, to abate both on-chip peak temperature and thermal gradient by developing thermal force and padding techniques cooperated with rough legalization in the force-directed global placement. Thermal padding is firstly adopted to reduce local power density. To make use of thermal force, we use the thermal gain basis to fast and accurately capture the temperature distribution of a placement, and effectively calculate the thermal contribution of cells based on the thermal locality. Then, we utilize the proposed innate thermal force assessed through thermal criticality and capabilities to spread cells away from hotspots. With the thermal gain basis, ThermPL can efficiently obtain the thermal profile of placement with the maximum error of 0.65% compared with a commercial tool. Experimental results show that ThermPL can provide 7% and 19% reduction on average in peak temperature and thermal gradient respectively within only 4.6% wirelength overhead.