ThermPL: Thermal-aware Placement Based on Thermal Contribution and Locality

Abstract

This work builds a thermal-aware placer, ThermPL, to abate both on-chip peak temperature and thermal gradient by developing thermal force and padding techniques cooperated with rough legalization in the force-directed global placement. Thermal padding is firstly adopted to reduce local power density. To make use of thermal force, we use the thermal gain basis to fast and accurately capture the temperature distribution of a placement, and effectively calculate the thermal contribution of cells based on the thermal locality. Then, we utilize the proposed innate thermal force assessed through thermal criticality and capabilities to spread cells away from hotspots. With the thermal gain basis, ThermPL can efficiently obtain the thermal profile of placement with the maximum error of 0.65% compared with a commercial tool. Experimental results show that ThermPL can provide 7% and 19% reduction on average in peak temperature and thermal gradient respectively within only 4.6% wirelength overhead.