Browsing by Author "Hong, Hao-Chiao"

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10GSamples/s, 4-bit, 1.2V, design-for-testability ADC and DAC in 0.13 mu m CMOS technology
(2007)
Liang, Sheng-Chuan
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Huang, Ding-Jyun
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Ho, Chen-Kang
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Hong, Hao-Chiao
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電控工程研究所
This paper demonstrates a 10GS/s, 4-bit, flash analog-to-digital converter (ADC) and current-steering digital-to-analog converter (DAC) pair for the design or advanced serial-link transceivers. Current mode logic (CML) gates are used to alleviate the severe power bouncing. The active feedback amplifiers, CML, and wave-pipelining technique help achieve the ultimate 10 GHz sampling rate. A design-for-testability circuit using the digital loop-back scheme is added to address the difficulty of at-speed measurements. The experimental results show that the cascaded ADC and DAC pair achieves a 27.3 dBc spurious-free dynamic range and a 25.0 dB signal-to-noise ratio with the 1.11 GHz, -1 dBm stimulus. It corresponds to an ENOB of 3.86 bits. The test chip totally consumes 420 mW from a 1.2V supply. The areas of the ADC and DAC are 0.1575 mm(2) and 0.0636 mm(2), respectively in 0.13 mu m CMOS technology.
14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability
(2014-06-01)
Hong, Hao-Chiao
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Chen, Yung-Shun
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Fang, Wei-Chieh
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電機資訊學士班
;
電控工程研究所
This paper presents the design and test of a 14 GSps, four-bit data converter pair in 90 nm CMOS suitable for implementing advanced serial links. The data converter pair consists of a noninterleaved flash analog-to-digital converter (ADC) and a noninterleaved current-steering digital-to-analog converter (DAC). Both the converter designs adopt the wave-pipelining technique to increase the available signal settling time. Through detailed analysis, we show that cascading three active feedback preamplifiers to implement the cores of the comparators in the ADC balances the power budget and the design difficulty when we push the sampling rate to the process limit. Current mode logic gates are used to alleviate the power bouncing issue. To address the difficulty and high cost of testing the extremely high-speed converters, the design embeds the simple design-for- testability circuits cooperating with the on-chip resources to provide two cost-effective test modes. The first test mode cascades the ADC and DAC so that they can be tested at the rated speed without the need of a very high speed logic analyzer. The second test mode enables the eye diagram tests by shuffling the digital outputs of ADC as the inputs of the DAC instead of adopting conventional linear feedback shift register. The experimental results show that the cascaded ADC and DAC pair achieves a 31.0 dBc spurious-free dynamic range and a 25.9 dB signal-to-noise-and-distortion ratio with a 1.11 GHz, -1 dBFS stimulus at 14 GSps. The ADC and DAC consume 214 mW and 85 mW from a 1.0-V supply and occupy 0.1575 mm(2) and 0.0636 mm(2), respectively.
A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications
(2018-01-01)
Hong, Hao-Chiao
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Chiu, Yi
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電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents a 10-bit SAR ADC operating at a supply voltage (VDD) of 0.225 V and down to 0.2 V for self-sustainable IoT applications. We propose an ultra-low VDD temperature-compensated bias current generator for biasing the comparator against temperature variation to address the temperature-dependent issue of the MOSFETs operating in the subthreshold region. In addition, the design fixes the positive input terminal of the comparator at VDD to bias the input transistor pair of the comparator with a sufficient voltage headroom at such a low VDD. The double-boosted with leakage reduction sampling switch is also proposed to address the severe leakage issue at low sampling rates. A test chip has been fabricated in 180-nm CMOS. The ADC core occupies only 0.024 mm(2). Measurement results show that at 0.225V, the DNL and INL are within +1.04/-0.66 and +0.97/-1.04 LSB in the rail-to-rail input range, respectively. The measured peak SNDR with the Nyquist input frequency is 49.8 dB at 450 S/s and 0.225V. The whole ADC totally consumes 0.85 nW at 0.225 V including the circuit leakages. It corresponds to an FoM of 8.0 fJ/conv.-step.
A 17-nW, 0.5V, 500S/s, Rail-to-Rail SAR ADC with 8.1 Effective Number of Bits
(2014-01-01)
Kuo, Rong-Zhou
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Hong, Hao-Chiao
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電控工程研究所
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Institute of Electrical and Control Engineering
This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 mu m CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.
A 6-GS/s, 6-bit, At-speed Testable ADC and DAC Pair in 0.13 mu m CMOS
(2009)
Ho, Chen-Kang
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Hong, Hao-Chiao
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper demonstrates a 6-GS/s 6-bit flash ADC and current-steering DAC pair in 0.13 mu m CMOS. Averaging and interpolating techniques are applied to reduce the offsets and to save the power of the ADC. Current mode logics are used to achieve a high speed and to overcome the severe power bouncing issue. Design-for-testability circuits are added to conduct the at-speed tests by internally cascading the ADC and DAC. The cascaded ADC and DAC pair clocked at 6GHz achieves a 37.0 dB signal-to-noise ratio and a 26.0 dBc spurious-free dynamic range with the -1 dBFS, 502 MHz stimulus. The ADC and DAC consumes 655 mW and 115 mW from a 1.2-V supply, respectively.
A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC
(2007-10-01)
Hong, Hao-Chiao
;
Lee, Guo-Ming
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電控工程研究所
;
Institute of Electrical and Control Engineering
An 8-bit successive approximation (SA) analog-to-digital converter (ADC) in 0.18 mu m CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 mu W in the test, corresponding to a figure of merit of 65 fJ/conversion-step.
A Built-in-Self-Test I sigma-Delta ADC Prototype
(2009-06-01)
Hong, Hao-Chiao
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Liang, Sheng-Chuan
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Song, Hong-Chin
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電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a built-in-self-test (BIST) I - pound Delta ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability I - pound Delta modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard -aEuro parts per thousand 6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.
A cost effective BIST second-order Sigma-A-modulator
(2008)
Hong, Hao-Chiao
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Liang, Sheng-Chuan
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Song, Hong-Chin
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電控工程研究所
;
Institute of Electrical and Control Engineering
This paper demonstrates a cost effective built-in-self-test (BIST) E-A modulator prototype. The BIST prototype is composed of a design-for-digital-testability second-order E-A modulator chip and a FPGA which implements the digital BIST functions. The BIST system is based on the modified control sine wave fitting (MCSWF) procedure. Different from the con- ventional analysis method using Fast Fourier Transform (FFT), this implementation requires neither any parallel multiplier nor complex CPU/DSP and bulky memory. Measurement results show that the BIST prototype gives a signal-to-noise-and-distortion ratio (SNDR) result of 74.3 dB which is within 0.3 dB comparing with the FFT counterpart. The proposed BIST implementation achieves the advantages of compact hardware, high accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.
A cost effective output response analyzer for Sigma-Delta modulation based BIST systems
(2006)
Hong, Hao-Chiao
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Liang, Sheng-Chuan
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電控工程研究所
;
Institute of Electrical and Control Engineering
A cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using Fast Fourier Transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) infrequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications.
A Cost-Effective Angle Demodulator IC for Path Matched Differential Interferometry Based Sensors
(2014)
Hong, Hao-Chiao
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Chen, Yun-Tse
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Hung, Shao-Feng
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Wu, Chin-Cheng
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Chiu, Yi
The angle demodulator (ADM) is a key component for the path matched differential interferometry (PMDI) sensors. Conventional ADMs require tens of operational amplifiers (OPAMPs) and bulky capacitors and resistors, making them diflicult to be realized as integrated circuits (ICs). This paper presents the first ADM IC design that requires only one OPAMP and thus saves significant area and power. In addition, this novel ADM design tolerates a wide range of modulation depth of the optical interferometer of the PMDI sensors. As a result, the yield of the PMDI sensor significantly increases. A test chip has been designed and successfully verified in 0.18-mu m CMOS. The active area of the proposed circuits is only 476 by 368 mu m(2) and it consumes only 6.26 mW.
A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles
(2014)
Hung, Shao-Feng
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Lin, Long-Yi
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Hong, Hao-Chiao
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電機學院
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College of Electrical and Computer Engineering
The battery management system (BMS) is substantial in diagnosing and controlling the battery modules of emerging electric vehicles (EVs). This paper presents a cost-effective stimulus generator for characterizing the communication channels between the BMS host controller and the battery cells. The characterization data are useful to enhance the reliability of the communication. The proposed stimulus generator only consists of a digital oscillator, a reconfigurable digital Sigma-Delta modulator, and an output driver. The all-digital design saves the power and the hardware cost. The digital oscillator provides digital sine waves with well-controlled frequency and amplitude. The proposed reconfigurable digital Sigma-Delta modulator allows generating pulse-density-modulated (PDM) bit-streams of particular frequencies that cover the whole band of interest. Hence, the test accuracy is no less than that of conventional sinusoidal waves. Simulation results show that the generated stimuli have very high narrow-band SNRs that is essential to test the frequency responses of the channels.
A Decorrelating Design-for-Digital-Testability Scheme for Sigma - Delta Modulators
(2009-01-01)
Hong, Hao-Chiao
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Liang, Sheng-Chuan
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電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a novel decorrelating design-for-digital-testability (D(3)T) scheme for Sigma - Delta modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Sigma - Delta modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than - 5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D(3)T scheme has the potential to test moderate nonlinearity. The proposed D(3)T scheme has the advantages or achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.
A design-for-digital-testability circuit structure for Sigma-Delta modulators
(2007-12-01)
Hong, Hao-Chiao
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電控工程研究所
;
Institute of Electrical and Control Engineering
A design-for-digital-testability (DfDT) switched-capacitor circuit structure for testing Sigma-Delta modulators with digital stimuli is presented to reduce the overall testing cost. In the test mode, the DfDT circuits are reconfigured as a one-bit digital-to-charge converter to accept a repetitively applied Sigma-Delta modulated bit-stream as its stimulus. The single-bit characteristic ensures that the generated stimulus is nonlinearity free. In addition, the proposed DfDT structure reuses most of the analog components in the test mode and keeps the same loads for the operational amplifiers as if they were in the normal mode. It thereby achieves many advantages including lower cost, higher fault coverage, higher measurement accuracy, and the capability of performing at-speed tests. A second-order Sigma-Delta modulator was designed and fabricated to demonstrate the effectiveness of the DfDT structure. Our experimental results show that the digital test is able to measure a harmonic distortion lower than -106 dBFS. Meanwhile, the dynamic range measured with the digital stimulus is as high as 84.4 dB at an over-sampling ratio of 128. The proposed DfDT scheme can be easily applied to other types of Sigma-Delta modulators, making them also digitally testable.
A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation
(2018-01-01)
Wu, Meng-Shuan
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Hong, Hao-Chiao
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電控工程研究所
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Institute of Electrical and Control Engineering
This paper proposes a digital background calibration scheme for calibrating the linear and the third-order nonlinear gain errors of the residue amplifiers (RAs) in pipelined ADCs. It is based on a novel multiple-correlation estimation (MCE) technique. We define two correction parameters relating to the gain errors of the RA under calibration. By alternately injecting two bi-level pseudo-random signals with designated amplitudes to the RA through the sub-DAC, the desired correction parameters are estimated according to the correlations of the backend ADC's outputs and the injected pseudo-random signals. Two least-mean-square (LMS) loops are adopted to find and to track the optimal values of the correction parameters. Simulation results of a 12-bit pipelined ADC show that the SNDR is improved from 46.4 dB to 73.4 dB with the help of the proposed calibration design. The proposed calibration scheme has the advantages of simple implementation, no restriction on the input signal of the ADC, fast settling, and running in background.
A Digitally Testable Sigma - Delta Modulator Using the Decorrelating Design-for-Digital-Testability
(2011-03-01)
Liang, Sheng-Chuan
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Hong, Hao-Chiao
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電機工程學系
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Department of Electrical and Computer Engineering
This paper demonstrates a digitally testable second-order Sigma - Delta modulator. The modulator under test (MUT) employs the decorrelating design-for-digital-testability (D(3)T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D(3)T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Sigma - Delta modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same Sigma - Delta modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, the D(3)T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the -3.2 dBFS test. The analog hardware overhead of the D(3)T MUT only consists of 13 switches.
A Fast-Locking All-Digital Phase Locked Loop in 90nm CMOS for Gigascale Systems
(2014-01-01)
Chen, Yi-Wei
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Hong, Hao-Chiao
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper presents an all-digital phase locked loop (ADPLL) design that features fast frequency locking and a wide tuning range. The all-digital implementation makes the design well suit Gigascale systems in advanced technology. The proposed ADPLL first uses the Regula Falsi method to fast lock the output frequency. Then, a frequency tracking (FT) loop is enabled to stabilize the output frequency against environmental disturbance as conventional PLL does. A test chip has been fabricated in 90 nm CMOS. Measurement results show the proposed ADPLL locks in 7 cycles and provides output frequencies ranging from 460.1 MHz to 6.117 GHz.
A Fully Integrated BIST Delta Sigma ADC Using the In-Phase and Quadrature Waves Fitting Procedure
(2014-12-01)
Hung, Shao-Feng
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Hong, Hao-Chiao
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper demonstrates a fully integrated builtin self-test (BIST) Delta Sigma analog-to-digital converter (ADC) based on the proposed in-phase and quadrature waves fitting (IQWF) procedure. The IQWF procedure enables accurately measuring the phases and amplitudes of test responses so as to enhance the test accuracy of the BIST circuitry. The all-digital BIST circuitry, with on-chip stimulus generator and response analyzer, conducts single-tone functional tests to test for the ADCs characterization results such as signal-to-noise-and-distortion ratio (SNDR), dynamic range (DR), frequency response, input-referred offset, and gain error. Since the IQWF procedure is performed successively in real time, the BIST circuitry does not need huge memory to store all the output samples like conventional fast Fourier transform (FFT) analysis does. The overall hardware overhead only consists of 16.6 k digital gates. The fully integrated BIST Delta Sigma ADC has been fabricated in 0.18-mu m CMOS. Measurement results show that the BIST circuitry reports a peak SNDR of 88.0 dB and a DR of 92.6 dB while the corresponding FFT-based analog tests result in 88.8 and 94.1 dB, respectively. Particularly, the BIST circuitry achieves a test bandwidth as wide as the ADCs 20-kHz rated bandwidth, which is the widest to the best of our knowledge. The proposed BIST ADC can be tested without costly external test resources and is thus well suited for the applications in which conventional test resources are not available such as 3-D ICs.
A Fully Integrated Built-In Self-Test Sigma-Delta ADC Based on the Modified Controlled Sine-Wave Fitting Procedure
(2010-09-10)
Hong, Hao-Chiao
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Su, Fang-Yi
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Hung, Shao-Feng
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電機工程學系
;
Department of Electrical and Computer Engineering
This paper demonstrates the first fully integrated built-in self-test (BIST) Sigma-Delta analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a second-order design-for-digital-testability Sigma-Delta modulator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and eliminate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13 300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST Sigma-Delta ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT.
A fully-settled linear behavior plus noise model for evaluating the digital stimuli of the design-for-digital-testability Sigma-Delta modulators
(2007-12-01)
Hong, Hao-Chiao
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電控工程研究所
;
Institute of Electrical and Control Engineering
Evaluating the digital stimuli used in the design-for-digital-testability (DfDT) Sigma-Delta modulator is a time-consuming task due to its oversampling and non-linear nature. Although behavioral simulations can substantially improve the simulation speed, conventional behavioral models fail to provide accurate enough signal-to-noise ratio (SNR) predictions for this particular application. In this paper, a fully-settled linear behavior plus noise (FSLB+N) model for the DfDT Sigma-Delta modulator is presented to improve both the accuracy and the speed of the behavioral simulations. The model includes the following parameters: the finite open-loop gains, the offsets, the finite output swings, the flicker noise of the operational amplifiers (OPAMPs), as well as the thermal noises of the switched capacitors, the OPAMPs, and the reference supplies. With the proposed model, the behavioral simulation results demonstrate a high correlation with the measurement data. On average, the SNR difference between the simulation and the measurement is -1.1 dB with a maximum of 0.05 dB and a minimum of -2.2 dB. Comparing with the circuit-level simulation using HSPICE, the behavioral simulation with the FSLB+N model is 1,190,000 times faster. The proposed model not only can be used for evaluating the digital stimulus candidates, but also can be applied to system-level simulations of the mixed-signal design with an embedded DfDT Sigma-Delta modulator.
A Low-Cost Output Response Analyzer for the Built-in-Self-Test Sigma-Delta Modulator Based on the Controlled Sine Wave Fitting Method
(2009)
Hung, Shao-Feng
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Hong, Hao-Chiao
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Liang, Sheng-Chuan
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper proposes I low-cost output response analyzer (ORA) for the built-in-self-test (BIST) Sigma-Delta ADC based on the controlled sine wave fitting (CSWF) method. The ADC under test (AUT) is composed of a design-for-digital-testability (DfDT) second-order E-A modulator and a decimation filter. The CSWF BIST procedure requests in ORA to accept the output of the AUT and calculates the offset, the amplitude of the stimulus tone response, and the total-harmonic-distortion-and-noise (THD+N) power in three successive BIST steps respectively. Each BIST step needs all accumulator to conduct the specified BIST function. By sharing an accumulator for every BIST step, the proposed ORA design contains only 1.9k gates without loss of computational accuracy. The hardware is only 34% of the original design. Simulation results show that the proposed ORA presents accurate SNDR results for the 1 kHz tests.