Browsing by Author "Hsiao, TY"

Now showing 1 - 8 of 8

A new development environment for an event-based distributed system
(2003-08-01)
Hsiao, TY
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Perng, NC
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Lo, W
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Chang, YS
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Yuan, SM
The rapid growth of data exchange on the Internet has created many critical problems that require an answer. Traditional data exchange systems based on client/server communication models are less scalable and incur especially high maintenance cost in the data exchange domain. For these reasons, many researchers have switched their interest to asynchronous communication models. Although Message-Oriented Middleware (MOM) is a middle-tier infrastructure that links operating systems and applications, such asynchronous communication APIs supported by middleware vendors are usually hard to use. For these reasons, in this study, we present a new development environment for asynchronous communication platforms which we term Ghostwriter. The keyword for our development environment is 'easy', that is, easy to,use, easy to develop, and easy to deploy. Therefore, many researchers have switched their interest to asynchronous communication models. In addition, learning about and implementing the functions of the asynchronous communication's clients in Ghostwriter environment is simple. Other benefits are a lower technical learning curve, help for concentrate on system design, has easily reusable components, and easily integrated applications. (C) 2003 Elsevier Science B.V. All rights reserved.
An AS-DSP for forward error correction applications
(2005)
Hsiao, TY
;
Lin, CC
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Chang, HC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
An application specific digital signal processor for channel coding is presented. The vector operations can improve both the performance of memory accesses and program code density. The special function units and datapaths for channel decoding accelerate the decoding speed and facilitate algorithm implementation. The processor had been fabricated in a 0.18 mu m CMOS 1P6M technology. The 2 chip size is 7.73 mm(2) including 18k bits embedded memory, and the power consumption is 141 mW while decoding Reed-Solomon code and convolutional code. In contrast with general purpose processor designs, the results show this chip has at least 50% improvement in code density and 66% data rate enhancement.
An asynchronous high confident information interchange infrastructure
(2001)
Hsiao, TY
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Shen, RK
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Liang, KC
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Perng, NC
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Yuan, SM
Data exchange by networks is getting important due to the growing of Internet. One of the popular architectural styles for distributed, loosely-coupled, heterogeneous network systems is a structure based on event generation, observation and notification. In this paper, we propose the event-based data exchange model to solve the problems encountered by traditional data exchange systems, We provide two main contributions to the study of data exchange system. First, we cover the surveys of data exchange systems currently on the market as well as the proposed architecture, MEDEA(Model of Event-based Data Exchange Architecture). Second, XML plays an important role in data exchange system now. We also propose a solution, which is called CODEX(Content-Oriented Data EXchange model), combines the features of mark-up language XML and the architecture of MEDEA. CODEX contains functions like primitive data type checking, data classification, data filtering, user identity and user filtering.
An asynchronous message exchange system on CORBA
(2000)
Hsiao, TY
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Lo, WT
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Yuan, SM
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資訊工程學系
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Department of Computer Science
Data exchange by networks is getting important due to the growing of Internet. One of the popular architectural styles for distributed, loosely-coupled, heterogeneous network systems is a structure based on event generation, observation and notification. Based on the event service and the naming service defined by OMG (Object Management Group), we build an efficient and Internet-scale event-driven data exchange architecture on CORBA. Asynchronous Message Exchange System (AMES) provides asynchronous publish/subscriber communication model and can communicate with legacy systems easily. This system was developed based on Java programming language and Inprise Visibroker for Java product families.
Efg1 involved in drug resistance by regulating the expression of ERG3 in Candida albicans
(2005-03-01)
Lo, HJ
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Wang, JS
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Lin, CY
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Chen, CG
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Hsiao, TY
The ERG3 gene in Candida albicans was identified as a gene whose mRNA level was higher in the cph1/cph1 efg1/efg1 double mutant than in the wild-type cells. Further study showed that Efg1, but not Cph1, negatively regulated ERG3. Mutations in EFG1 consistently increased the susceptibility of the cells to antifungal agents.
FJM: a high performance Java Message Library
(2003)
Hsiao, TY
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Cheng, MC
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Chiao, HT
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Yuan, SM
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資訊工程學系
In this paper, we presented an IP-multicast-based Java Message Service implementation called FJM (Fast Java Messaging) Library. We discussed its architecture, protocols, and implementation issues. For achieving better performance, we revised the original design of the FJM. The details of the refinement were also described in this paper. Then, we compared the performance of the both versions of the FJM with the performance of other JMS implementations. After our carefully design and tuning, in most cases, the revised version of the FJM can offer the highest throughput among the well-known industrial or open source JMS implementations. Therefore, FJM can be used in many innovative or mission critical cluster applications, such as massively multiplayer virtual worlds or military simulator.
Multi-level memory systems using error control codes
(2004)
Chang, HC
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Lin, CC
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Hsiao, TY
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Wu, JT
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Wang, TH
In this paper, the multi-level memory system using error control codes has been proposed. As compared with other approaches for 2(m)-level memory cells, our proposal features an effective grouping of several q-level memory cells with q > 2(m) in order to create parity bits of error control codes. Therefore, the proposed methodology can enhance both the yield and reliability without area penalty for multi-level memory systems. The BCH (72,64) code of correcting single error is presented for 5-level memory cells. In contrast to 2(2)-level memory cells, our proposal can improve yields from 61.58% to 99.92% for 16Mbit and make the mass production of 1Gbit memory practicable under the approximated model for StrataFlash(TM). Since our work was motivated from the use of q-level cells in substitution for 2(m)-level cells, not only multi-level flash memory, but also multi-level DRAM systems, can both benefit from our proposed methodology.
Practical middleware for massively multiplayer online games
(2005-09-01)
Hsiao, TY
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Yuan, SM
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資訊工程學系
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Department of Computer Science
A massively multiplayer online game (MMOG) lets thousands of players interact simultaneously within a virtual world via the Internet. Middleware plays an important role in the development of next-generation MMOGs, which must be built on platforms that address not only the service aspect, but also code maintainability and development for programmers. The authors' compact, high-performance message-oriented middleware has a code-generation programming model that is designed to address many of these problems.