Multi-level memory systems using error control codes

Abstract

In this paper, the multi-level memory system using error control codes has been proposed. As compared with other approaches for 2(m)-level memory cells, our proposal features an effective grouping of several q-level memory cells with q > 2(m) in order to create parity bits of error control codes. Therefore, the proposed methodology can enhance both the yield and reliability without area penalty for multi-level memory systems. The BCH (72,64) code of correcting single error is presented for 5-level memory cells. In contrast to 2(2)-level memory cells, our proposal can improve yields from 61.58% to 99.92% for 16Mbit and make the mass production of 1Gbit memory practicable under the approximated model for StrataFlash(TM). Since our work was motivated from the use of q-level cells in substitution for 2(m)-level cells, not only multi-level flash memory, but also multi-level DRAM systems, can both benefit from our proposed methodology.