Browsing by Author "Hsieh, Chien-Sheng"

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Investigation of programming charge distribution in nonoverlapped implantation nMOSFETs
(2006-10-01)
Jeng, Erik S.
;
Kuo, Pai-Chun
;
Hsieh, Chien-Sheng
;
Fan, Chen-Chia
;
Lin, Kun-Ming
Novel gate-to-drain nonoverlapped-implantation (NOI) nMOSFETs have been developed as potential multibit-per-cell nonvolatile-memory (NVM) devices. The lateral charge distribution of the NOI NVM device programmed by channel hot electron injection is investigated by charge-pumping (CP) techniques with presumed interface trap distributions. For the first time, the CP results have revealed the lateral charge distribution and trapping density at the NOI's programmed state. The maximum trapping charge density locates near its drain junction. The charge distribution is estimated about 90 nm in length and spread widely over the NOI region. Two-dimensional simulators with charge bars using the same charge trapping distribution confirm the experimental results by fitting their I-DS - V-G curves.
Performance improvement and scalability of nonoverlapped implantation nMOSFETs with charge-trapping spacers as nonvolatile memories
(2007-12-01)
Jeng, Erik S.
;
Chiu, Chia-Sung
;
Hon, Chih-Hsueh
;
Kuo, Pai-Chun
;
Fan, Chen-Chia
This paper explores gate-to-source/drain nonoverlapped implantation (NOI) devices that function as nonvolatile memories (NVMs) by trapping charges in the silicon nitride spacers. These NOI nMOSFET devices with improved NVM characteristics were simulated and demonstrated. For a 0.8 V shift in the threshold voltage, the programming and erasing speeds of NOI devices are as fast as 40 and 60 mu s, respectively. Improvements of other related NVM characteristics, including charge retention and cycling endurance,, are reported. Finally, the scalability of NOI devices is simulated and discussed.