Performance improvement and scalability of nonoverlapped implantation nMOSFETs with charge-trapping spacers as nonvolatile memories

Abstract

This paper explores gate-to-source/drain nonoverlapped implantation (NOI) devices that function as nonvolatile memories (NVMs) by trapping charges in the silicon nitride spacers. These NOI nMOSFET devices with improved NVM characteristics were simulated and demonstrated. For a 0.8 V shift in the threshold voltage, the programming and erasing speeds of NOI devices are as fast as 40 and 60 mu s, respectively. Improvements of other related NVM characteristics, including charge retention and cycling endurance,, are reported. Finally, the scalability of NOI devices is simulated and discussed.