標題: | Performance improvement and scalability of nonoverlapped implantation nMOSFETs with charge-trapping spacers as nonvolatile memories |
作者: | Jeng, Erik S. Chiu, Chia-Sung Hon, Chih-Hsueh Kuo, Pai-Chun Fan, Chen-Chia Hsieh, Chien-Sheng Hsu, Hui-Chun Chen, Yuan-Feng 電信工程研究所 Institute of Communications Engineering |
關鍵字: | charge trapping;nonoverlapped implantation (NOI);nonvolatile memory (NVM) |
公開日期: | 1-十二月-2007 |
摘要: | This paper explores gate-to-source/drain nonoverlapped implantation (NOI) devices that function as nonvolatile memories (NVMs) by trapping charges in the silicon nitride spacers. These NOI nMOSFET devices with improved NVM characteristics were simulated and demonstrated. For a 0.8 V shift in the threshold voltage, the programming and erasing speeds of NOI devices are as fast as 40 and 60 mu s, respectively. Improvements of other related NVM characteristics, including charge retention and cycling endurance,, are reported. Finally, the scalability of NOI devices is simulated and discussed. |
URI: | http://dx.doi.org/10.1109/TED.2007.908598 http://hdl.handle.net/11536/10039 |
ISSN: | 0018-9383 |
DOI: | 10.1109/TED.2007.908598 |
期刊: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 54 |
Issue: | 12 |
起始頁: | 3299 |
結束頁: | 3307 |
顯示於類別: | 期刊論文 |