Browsing by Author "Hsieh, Ing-Jar"

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Formation of inverted-pyramid structure by modifying laser processing parameters and acid etching time
(2011)
Lin, Je-Wei
;
Liu, En-Ting
;
Wu, Chien-Hung
;
Hsieh, Ing-Jar
;
Chao, Tien-Sheng
This paper is to investigate the possibility to fabricate the inverted-pyramid structure on silicon wafer base solar cell by using laser scribing technology. The UV spectrometer and SEM had also been used to observe the reflectance and microstructure of the wafer surface. In this experiment, a Q-switched Nd:YAG laser operating at wavelength of 1064nm is used to scribe on the p-type wafer surface to produce inverted-pyramid structure. In order to remove the laser damage, we used acid etching and Alkaline etching solutions to smooth the damage region and inverted pyramid structure formed, simultaneously.
Formation of iridium nanocrystals with highly thermal stability for the applications of nonvolatile memory device with excellent trapping ability
(2010-10-04)
Wang, Terry Tai-Jui
;
Chu, Chang-Lung
;
Hsieh, Ing-Jar
;
Tseng, Wen-Shou
;
材料科學與工程學系
This paper presents the formation of iridium nanocrystals (Ir-NCs) embedded in SiO(2) matrix and it can be used for potential applications of nonvolatile memory devices. The NC formation is investigated by varying Ir film thickness; and the thermal agglomeration is also studied by applying various annealing temperatures and process time. The results of systematic characterization including capacitance-voltage, transmission electron microscopy, and x-ray photoelectron spectroscopy show that the high work-function (5.27 eV) metallic-NCs have a highly thermal stability (up to 900 degrees C) and the resulted Al/SiO(2)/Ir-NCs/SiO(2)/Si/Al stack can have a good retention ability and significant hysteresis window of 17.4 V. (C) 2010 American Institute of Physics. [doi:10.1063/1.3498049]
Formation of iridium nanocrystals with highly thermal stability for the applications of nonvolatile memory device with excellent trapping ability
(2010-10-04)
Wang, Terry Tai-Jui
;
Chu, Chang-Lung
;
Hsieh, Ing-Jar
;
Tseng, Wen-Shou
;
材料科學與工程學系
This paper presents the formation of iridium nanocrystals (Ir-NCs) embedded in SiO(2) matrix and it can be used for potential applications of nonvolatile memory devices. The NC formation is investigated by varying Ir film thickness; and the thermal agglomeration is also studied by applying various annealing temperatures and process time. The results of systematic characterization including capacitance-voltage, transmission electron microscopy, and x-ray photoelectron spectroscopy show that the high work-function (5.27 eV) metallic-NCs have a highly thermal stability (up to 900 degrees C) and the resulted Al/SiO(2)/Ir-NCs/SiO(2)/Si/Al stack can have a good retention ability and significant hysteresis window of 17.4 V. (C) 2010 American Institute of Physics. [doi:10.1063/1.3498049]
Ir Nanocrystals on Asymmetric Si(3)N(4)/SiO(2) Tunneling Layer with Large Memory Window for Nonvolatile Memory Application
(2011-04-01)
Wang, Terry Tai-Jui
;
Chen, Chao-Jui
;
Teng, I-Ju
;
Hsieh, Ing-Jar
;
Kuo, Cheng-Tzu
The capacitance-voltage measurements and microstructures of Iridium-nanocrystals embedded in two main stack devices of "Al/SiO(2)/Ir-NCs/SiO(2)/Si-Sub/Al" and "Al/SiO(2)/Ir-NCs/Si(3)N(4)/SiO(2)/SiSub/Al" have been compared for the application of nonvolatile memory. It has been demonstrated that the device performance of Si(3)N(4)/SiO(2) tunneling bi-layer (former stack) is much better than the single SiO(2) tunneling layer in terms of program/erase (P/E) efficiency and memory window size (up to 12.6 V at +/-10 V sweeping voltages), though 5% degrade in data retentions. Furthermore, endurances of two devices can stand 10(4) cycles without failure under P/E stressing condition of +/-9 V, 100 ms.
Ir Nanocrystals on Asymmetric Si3N4/SiO2 Tunneling Layer with Large Memory Window for Nonvolatile Memory Application
(2011-04-01)
Wang, Terry Tai-Jui
;
Chen, Chao-Jui
;
Teng, I-Ju
;
Hsieh, Ing-Jar
;
Kuo, Cheng-Tzu
The capacitance-voltage measurements and microstructures of Iridium-nanocrystals embedded in two main stack devices of "Al/SiO2/Ir-NCs/SiO2/Si-Sub/Al" and "Al/SiO2/Ir-NCs/Si3N4/SiO2/SiSub/Al" have been compared for the application of nonvolatile memory. It has been demonstrated that the device performance of Si3N4/SiO2 tunneling bi-layer (former stack) is much better than the single SiO2 tunneling layer in terms of program/erase (P/E) efficiency and memory window size (up to 12.6 V at +/-10 V sweeping voltages), though 5% degrade in data retentions. Furthermore, endurances of two devices can stand 10(4) cycles without failure under P/E stressing condition of +/-9 V, 100 ms.
Iridium Nanocrystal Thin-Film Transistor Nonvolatile Memory with Si(3)N(4)/SiO(2) Stack of Asymmetric Tunnel Barrier
(2011-05-01)
Wang, Terry Tai-Jui
;
Lu, Tien-Lin
;
Wu, Chien-Hung
;
Liu, Yu-Cheng
;
Hung, Shih-Wei
Iridium nanocrystals (Ir-NCs) lying on the Si(3)N(4)/SiO(2) tunneling layer have been demonstrated and Ir-NC-assisted thin-film transistor nonvolatile memory devices were successfully developed. Results show that Ir-NCs with a number density of similar to 6 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge trapping centers. Owing to the asymmetric SiO(2)/Si(3)N(4) tunneling layer that increases programming/erasing efficiency, a significant memory window of 5.5 V has potential to be applied to multibit memory devices. Furthermore, after 10(4) s, the memory window is still about 4.0 V in logic states. (C) 2011 The Japan Society of Applied Physics
Iridium Nanocrystal Thin-Film Transistor Nonvolatile Memory with Si3N4/SiO2 Stack of Asymmetric Tunnel Barrier
(2011-05-01)
Wang, Terry Tai-Jui
;
Lu, Tien-Lin
;
Wu, Chien-Hung
;
Liu, Yu-Cheng
;
Hung, Shih-Wei
Iridium nanocrystals (Ir-NCs) lying on the Si3N4/SiO2 tunneling layer have been demonstrated and Ir-NC-assisted thin-film transistor nonvolatile memory devices were successfully developed. Results show that Ir-NCs with a number density of similar to 6 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge trapping centers. Owing to the asymmetric SiO2/Si3N4 tunneling layer that increases programming/erasing efficiency, a significant memory window of 5.5 V has potential to be applied to multibit memory devices. Furthermore, after 10(4) s, the memory window is still about 4.0 V in logic states. (C) 2011 The Japan Society of Applied Physics
Nickel Nanocrystals Embedded in Metal-Alumina-Nitride-Oxide-Silicon Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor for Low-Voltage Nonvolatile Memory Application
(2011-06-01)
Wang, Terry Tai-Jui
;
Liu, Yu-Cheng
;
Wu, Chien-Hung
;
Lu, Tien-Lin
;
Hsieh, Ing-Jar
In this work, a nickel nanocrystal (Ni-NC) assisted metal-alumina-nitride-oxide-silicon (MANOS) thin-film transistor (TFT) nonvolatile memory (NVM) was fabricated by a standard low temperature polycrystalline silicon (LTPS) TFT process. The size range and density of Ni-NCs were approximately 5-13 nm and 5 x 10(11) cm(-2), respectively. The programming/erasing (P/E) voltages are decreased down to -10 and +8 V, respectively, by the Fowler-Nordheim tunneling mechanism from gate injection. In this P/E voltage condition, a large memory window (similar to 4.2 V) was observed by current-voltage measurement. Then, the speed and voltages of P/E were measured and discussed completely. The data retention of the Ni-NC assisted MANOS-LTPS-TFT-NVM is extracted to be 1.62 V of memory window after 10(4) s. (C) 2011 The Japan Society of Applied Physics