Browsing by Author "Hsieh, Wei-Chih"

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Adaptive Power Control Technique on Power-Gated Circuitries
(2011-07-01)
Hsieh, Wei-Chih
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Hwang, Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
An adaptive power control (APC) system on power-gated circuitries is proposed. The core technique is a switching state determination mechanism as an alternative of critical path replicas. It is intrinsically tolerant of process, voltage, and temperature (PVT) variations because it directly monitors the behavior of VDDV node. The APC system includes a multi-mode power gating network, a voltage sensor, a variable threshold comparator, a slack detection block, and a bank of bidirectional shift registers. By dynamically configuring the size of power gating devices, an average of 56.5% unused slack resulted from worst case margins or input pattern change can be further utilized. A 32-64 bit multiply-accumulate (MAC) unit is fabricated using UMC 90-nm standard process CMOS technology as a test vehicle. The measurement results of test chips exhibit an average of 12.39% net power reduction. A 7.96 x leakage reduction is reported by power gating the MAC unit. For the 32-bit multiplier of MAC, the area and power overhead of proposed APC system are 5% and 1.08%, respectively. Most of the overhead is contributed by power gating devices and their control signal buffers.
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation
(2012-06-01)
Hsieh, Wei-Chih
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Hwang, Wei
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, an all digital push-pull linear voltage regulator is proposed that consists of a digital error detector, a voltage divider, a mode indicator, a pull device, and grouped push devices. The digital regulator is suitable for super-to near-threshold region operation by providing a variable output voltage that ranges from 0.5 to 1 V in steps of 0.1 V. The maximum load current is 100 mA for every output level. The current efficiency is 99.8% with only 164.5 mu A quiescent current on UMC 65-nm standard CMOS technology. A response time constraint is developed to provide a design guideline for (all) the digital control system. It describes the correlation between required speed of the digital control system, the output performance and the size of the decoupling capacitor. A time interleaving control technique is then proposed to have a tradeoff between output performance, quiescent current, and the size of decoupling capacitor.
Fully On-Chip Temperature, Process, and Voltage Sensors
(2010)
Chen, Shi-Wen
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Chang, Ming-Hung
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Hsieh, Wei-Chih
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Hwang, Wei
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電子與資訊研究中心
A process, voltage, and temperature (PVT) sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high accuracy, low power, and wide voltage range portable applications. Conventional temperature sensors rely on voltage/current ADC for digital output code conversion. The proposed temperature sensor generates a clock frequency proportional to the measured temperature, and converts the frequency into a corresponding digital code. The generated digital code is still under the influence of PVT variations. Two distinct sensors for voltage and process monitoring are also proposed to enhance temperature sensor environmental variation immunity. The property of zero temperature coefficient (ZTC) bias point is used to remove temperature effect. The proposed wide voltage range low power PVT sensor is designed in UMC 65nm bulk CMOS technology. It is capable of operating over a wide voltage range within 0.3V similar to V. The power consumption is no more than 3.7 mu W at 0.3V supply voltage and a high sample rate of 10k samples/sec. The temperature error is merely -0.8 similar to 0.8 degrees C.
High Efficiency Power Management System for Solar Energy Harvesting Applications
(2010)
Chang, Ming-Hung
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Wu, Jung-Yi
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Hsieh, Wei-Chih
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Lin, Shang-Yuan
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Liang, You-Wei
A high efficiency power management system for solar energy harvesting applications is proposed. The power management system receives power from photovoltaic (PV) cell and generate different voltage levels, they are 1V similar to 0.3V for analog circuitry and low power digital circuitry, -1.2V for super-cutoff technique in memory circuitry, and 10V for FLASH memory or I/O components. The great voltage varieties are suitable for green integrated regulator SoC electronics. The power management system also contains a rechargeable battery which is charged by multi-phase maximum power tracking (MPT) circuitry with the PV cell module. With the MPT circuitry, the power of PV cell can be regulated in the maximum power region. The average power efficiency of the MPT circuitry is up to 80%similar to 73%. All resultsare simulated in UMC 90nm bulk CMOS technology model.
IN-SITU SELF-AWARE ADAPTIVE POWER CONTROL SYSTEM WITH MULTI-MODE POWER GATING NETWORK
(2008)
Hsieh, Wei-Chih
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An in-situ self-aware adaptive power control (APC) system is presented in this paper. This APC system consists of a voltage sensor, a variable threshold comparator, slack detection circuits and control signal generators to control a set of bidirectional shift registers. The values stored in bidirectional shift registers are used to control the status of multi-mode power gating network. This APC system can suppress power consumption aggressively under different operating speeds. A 16-bit multiplier is implemented as a test bench along with the APC system in UMC 90nm CMOS technology. It exhibits more than 20% overall power reduction under the same speed criteria. The power and area overheads are only 3.64% and 7.36% respectively.
Low power on-chip current monitoring medium-grained adaptive voltage control
(2007)
Hsieh, Wei-Chih
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Hwang, Wei
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a novel low power on-chip current monitor is proposed for adaptive voltage control (AVC). Instead of tracking the delay of worst case critical path replica, current characteristic of target circuits is considered. The proposed current monitor distinguishes between the switching and stable state of the circuit by monitoring the current consumption. It has no negative impact on circuit speed with only less than 3 mu W power overhead. Using proposed low power on-chip current monitor, a medium-grained adaptive voltage control scheme is also presented. Traditional AVC applied a single (scaled) voltage satisfying critical path to the whole chip, wasting the power in non-critical paths. The medium-grained AVC exploits the unused slack in non-critical paths, which further discovers the power reduction potentiality that lies on non-critical paths. A different width multipliers example exhibits over 30% power reduction on non-critical paths. Simulations are all implemented in Berkeley Predictive 65nm technology [7].
Low Quiescent Current Variable Output Digital Controlled Voltage Regulator
(2010)
Hsieh, Wei-Chih
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Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a digital controlled push-pull linear voltage regulator is proposed. The designed regulator can provide a variable output voltage ranging from 0.5V to 1V in steps of 0.1V. It can supply a maximum of 100mA for each output level. A time interleaving control technique is also presented to enhance the output performance. By using UMC 65nm standard CMOS technology, the ripple of the output voltage when the load or output level changes is smaller than 10% of each specific output level. The current efficiency is 99.9% with only 126 mu A quiescent current.
Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications
(2013)
Chang, Ming-Hung
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Hsieh, Wei-Chih
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Wu, Pei-Chen
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Chuang, Ching-Te
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Chen, Kuan-Neng
In this work, a multi-layer hierarchical distributed power delivery architecture for TSV 3DIC is proposed. By decoupling global and local power networks, the proposed power delivery architecture can be flexibly configured for different power requests. The decoupled power architectures can also greatly reduce the required decoupling capacitor sizes for voltage stabilization. Meanwhile, a multi-threshold CMOS switched capacitor DC-DC converter with up to 78% power efficiency is implemented in 65nm CMOS for hierarchical distributed power delivery architecture. An adaptive power management technique is presented to work in the local power network to increase the power efficiency. The proposed multi-layer hierarchical distributed power delivery architecture is also very useful for the heterogeneous integration in 3DIC chips.