Browsing by Author "Hsieh, Yu-Sheng"

Now showing 1 - 7 of 7

3D Heterogeneous Integration Structure Based on 40 nm- and 0.18 mu m- Technology Nodes
(2015)
Hu, Yu-Chen
;
Lin, Chun-Pin
;
Hsieh, Yu-Sheng
;
Chang, Nien-Shyang
;
Gallegos, Anthony J.
In this paper, a simple process for high yield CMOS-compatible and heterogeneous integrated chip-to-chip structure without TSV is demonstrated. This scheme provides two chips consisted of the shortest interconnect path by Cu/Sn pillar bump and electroless nickel immersion gold (ENIG) pad bonding. One of the key technologies of 3D integration process is bump plating on the uneven topography. Since passivation layer covers the periphery of the top metal layer, subsequent electroplating process resulted to the increase in height of bump edge which is higher than bump center resulting in concave shape. A new and unique plating solution was developed to solve the issue during the electroplating pillar bump. Basic electrical characteristics including resistance and current leakage were investigated with reliability tests. The stable reliability tests results and excellent electrical performance show that the 3D heterogeneous integration structure is potentially applicable for 3D applications in the future.
Development and Electrical Investigation of Novel Fine-Pitch Cu/Sn Pad Bumping Using Ultra-Thin Buffer Layer Technique in 3D Integration
(2015)
Hsieh, Yu-Sheng
;
Chang, Yao-Jen
;
Chen, Kuan-Neng
;
電機學院
;
College of Electrical and Computer Engineering
A high yielding fine-pitch submicron Cu/Sn bonding scheme has been successfully demonstrated. With inserting the ultra-thin buffer layer, near sub-micron thickness Cu/Sn pad bonding can be achieved. The fine pitch Cu/Sn interconnects can be also further extended. The modified Kelvin feature in chip level and tens of thousands series interconnects per chip with a density of 3.4 x 10(5)/cm(2) in wafer level are fabricated and completely investigated on electrical characteristics. Several critical reliability assessments, such as TCT and unbias HAST, are also investigated the variation and standard error of the fine-pitch pad bonding scheme. With excellent mechanical properties, bonding quality, electrical and reliability results, the approach is suitable for future 3D vertical interconnects.
Development and Investigation of Ultra-Thin Buffer Layers Used in Symmetric Cu/Sn Bonding and Asymmetric Cu/Sn-Cu Bonding for Advanced 3D Integration Applications
(2017-01-01)
Chen, Hsiu-Chi
;
Kho, Yi-Tung
;
Huang, Yen-Jun
;
Hsieh, Yu-Sheng
;
Chang, Yao-Jen
In this work, a particular ultra-thin buffer layer (UBL) with various thickness ranging from 10 nm to 100 nm and different materials including Co, Ni, Pd and Ti is inserted between Cu/Sn to delay the interdiffusion prior to eutectic bonding. The efficacy of the buffer layer and the bonding quality are systematically conferred using microstructure imaging, material analysis, and electrical performance. In addition to symmetric Cu/Sn bonding with UBL, an asymmetric Cu/Sn-Cu bonding which is proposed to relieve the heat enhanced interdiffUsion issues thereby enhancing the reliability performance is demonstrated with the assistance of UBL technology.
Investigation and Optimization of Ultrathin Buffer Layers Used in Cu/Sn Eutectic Bonding
(2018-07-01)
Tang, Ya-Sheng
;
Chen, Hsiu-Chi
;
Kho, Yi-Tung
;
Hsieh, Yu-Sheng
;
Chang, Yao-Jen
Ultrathin buffer layers (UBLs) with varied thickness ranging from 10 to 100 nm and different materials were used in Cu/Sn eutectic bonding. A Cu/Sn film thinner than 2 mu m could fully react and became stiff and rough Cu-Sn intermetallic compound layer, which leads to failure bonding. Four kinds of semiconductor compatible materials including Ti, Pd, Co, and Ni were inserted between Cu/Sn to delay interdiffusion prior to eutectic bonding. In addition to symmetric Cu/Sn bonding with UBL, asymmetric Cu/Sn-Cu bonding scheme with 50-nm Ni UBL was demonstrated. With good mechanical properties, bonding quality, and electrical characteristics, the application of submicrometer Cu/Sn wafer-level bonding by assistance of buffering layer gives a promising and flexible platform for future 3-D integration applications.
Investigation of Low Temperature Cu/In Bonding in 3D Integration
(2015)
Hsieh, Yu-Sheng
;
Shen, Ting-Ting
;
Chien, Yu-San
;
Chen, Kuan-Neng
;
Shinozaki, Yuko
Low temperature (< 180 degrees C) Cu/In bonding scheme in wafer-level is successfully developed. The bonded sample represents robust bonding quality and passes mechanical tests. The inter-diffusion mechanism and IMC phases are investigated by EDX and EELS. In addition, the specific contact resistance of Cu/In chip is measured approximately 3 x 10(-9) Omega-cm(2) by modified Kelvin feature, demonstrating excellent electrical characteristics. Good stability is also observed from reliability tests, including current stressing, TCT and un-bias HAST. Therefore, this low temperature Cu/In bonding scheme provides a promising method for dense vertical interconnects.
Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application
(2015-06-01)
Chang, Yao-Yen
;
Ko, Cheng-Ta
;
Yu, Tsung-Han
;
Hsieh, Yu-Sheng
;
Chen, Kuan-Neng
Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson\'s equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 mu m. After presenting the fundamental C-V characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window (vertical bar V-ow vertical bar = 20 V) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge Q(ot) engineering in TSV oxide liner, neither considerations of the V-FB shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously.
Submicron Cu/Sn Bonding Technology With Transient Ni Diffusion Buffer Layer for 3DIC Application
(2014-11-01)
Chang, Yao-Jen
;
Hsieh, Yu-Sheng
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A submicron Cu/Sn bonding with transient Ni buffer layer at 225 degrees C is demonstrated to overcome current 5-mu m Cu/Sn physical limitation. The 10-nm Ni layer suppresses immense Cu/Sn interdiffusion during heating step prior to major bonding process. When the temperature is close to the Sn melting point, the Ni layer dissolves and molten Sn gives successful submicrometer Cu/Sn bonding. The excellent mechanical strength and electrical performance of this scheme show the great potential for future and highly dense 3D interconnects.