Development and Electrical Investigation of Novel Fine-Pitch Cu/Sn Pad Bumping Using Ultra-Thin Buffer Layer Technique in 3D Integration

Abstract

A high yielding fine-pitch submicron Cu/Sn bonding scheme has been successfully demonstrated. With inserting the ultra-thin buffer layer, near sub-micron thickness Cu/Sn pad bonding can be achieved. The fine pitch Cu/Sn interconnects can be also further extended. The modified Kelvin feature in chip level and tens of thousands series interconnects per chip with a density of 3.4 x 10(5)/cm(2) in wafer level are fabricated and completely investigated on electrical characteristics. Several critical reliability assessments, such as TCT and unbias HAST, are also investigated the variation and standard error of the fine-pitch pad bonding scheme. With excellent mechanical properties, bonding quality, electrical and reliability results, the approach is suitable for future 3D vertical interconnects.