Browsing by Author "Hsu, Chih-Chieh"

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Effect of Annealing Treatment on Performance of Ga2O3 Conductive-Bridging Random-Access Memory
(1970-01-01)
Gan, Kai-Jhih
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Liu, Po-Tsun
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Ruan, Dun-Bao
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Hsu, Chih-Chieh
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Chiu, Yu-Chuan
The effect of annealing on the performance of conductive-bridging random-access memory (CBRAM) with an amorphous gallium oxide (a-Ga2O3) switching layer has been studied. After annealing at 200 degrees C in N-2, a significant improvement of the bipolar resistive switching characteristics was observed. The a-Ga2O3 CBRAM showed good memory performance, with high switching endurance (up to 7.5 x 10(2) cycles) and high thermal stability. The resistive switching stability and electrical uniformity were also obviously improved. The memory window remained above 10(5) over 7.5 x 10(2) endurance cycles at 85 degrees C. Material characterization by x-ray photoelectron spectroscopy suggested that the improved uniformity of the resistive switching in the N-2-annealed Ga2O3 films may result from a higher density of oxygen vacancies. These results indicate great potential for such devices in future high-density nonvolatile memory applications.
Ferroelectric Characterization of Hafnium-Oxide-Based Ferroelectric Memories with Remote Nitrogen Plasma Treatments
(2019-01-01)
Lee, You-Ting
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Chen, Hsuan-Han
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Tung, Yi-Chun
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Shih, Bing-Yang
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Hsiung, Szu-Yen
In this paper, we experimentally demonstrated the advantage of remote nitrogen plasma on improving interface quality of HfO2-based ferroelectric devices. The remote nitrogen plasma not only reduces leakage current of gate stack to appropriately sustain the ferroelectricity during ferroelectric domain switching, but also effectively improve the ferroelectric fatigue to enhance endurance cycling performance.
Improved Thermal Stability and Stress Immunity in Highly Scalable Junctionless FETs Using Enhanced-Depletion Channels
(2018-12-05)
Liu, Chien
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Cheng, Chun-Hu
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Lin, Ming-Huei
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Shih, Yi-Jia
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Hung, Yu-Wen
In this work, we report a novel multi-PNPN-channel junctionless transistor with short channel length of 60nm. The multi-PNPN junctionless transistor exhibits the larger drive current of > 1 mu A/mu m, the steeper turn-on switching of 77 mV/decade, and the higher on/off current ratio of > 10(7) than the hybrid PN channel device under the same gate overdrive. The improved performance is mainly attributed to the enhanced depletion effect of multi-PNPN channel to optimize the electric field modification of surface p-channel. The stronger immunity to constant-voltage stress is also obtained for multi-PNPN channel due to the lower lateral electric field near drain side to reduce the impact ionization ratio. (C) 2018 The Electrochemical Society.
Investigation of Gate Oxide Short in FinFETs and the Test Methods for FinFET SRAMs
(2013)
Lin, Chen-Wei
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Chao, Mango C. -T.
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Hsu, Chih-Chieh
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods.
Investigation of Gate-Stress Engineering in Negative Capacitance FETs Using Ferroelectric Hafnium Aluminum Oxides
(2019-02-01)
Cheng, Chun-Hu
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Fan, Chia-Chi
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Liu, Chien
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Hsu, Hsiao-Hsuan
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Chen, Hsuan-Han
In this paper, we reported a ferroelectric HfAlOx negative capacitor transistor with gate-stress (GS) engineering. Compared to control device, the HfAlOx transistor with GS engineering percentage of I-ON enhancement and 27% V-T reduction under the assistance of the negative capacitance (NC) effect. The orthorhombic phase transition played a crucial role in realizing the NC effect. From the results of the material analysis, the theoretical Landau simulation and electrical measurement, we demonstrated that the GS is favorable for inducing orthorhombic phase crystallization of HfAlOx and stabilizing the NC effect, which shows the potential for the application of advanced technology node.
Investigation of Phase Transformation in HfO2 Ferroelectric Capacitor by Means of a ZrO2 Capping Layer
(2019-01-01)
Liu, Kuan-Wei
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Chen, Hsuan-Han
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Huang, Zhong-Ying
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Wang, Wei-Chun
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Fan, Yu-Chi
In this paper, the ferroelectric polarization effect of ZrO2 capping layer on HfO2 NUM capacitor was investigated. Based on crystallinity analysis, the phase transformation from monoclinic to orthorhombic phase in HfO2 film can be induced by a thin ZrO2 capping layer. The thickness of ZrO2 capping layer plays an important role in the ferroelectric polarization of HfO2 MFM capacitor. Compared to mixed HfZrO film, the stacked ZrO2/HfO2 film shows the advantage for suppressing the leakage issue during high-temperature ferroelectric phase transition.
Negative Capacitance CMOS Field-Effect Transistors with Non-Hysteretic Steep Sub-60mV/dec Swing and Defect-Passivated Multidomain Switching
(2019-01-01)
Liu, Chien
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Chen, Hsuan-Han
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Hsu, Chih-Chieh
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Fan, Chia-Chi
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Hsu, Hsiao-Hsuan
We demonstrated that the 2.5nm-thick HfAO(x) N-type NCFET based on defect-passivated multidomain switching can achieve a minimum 9 mV/dec subthreshold swing (SS), a negligible hysteresis of 1 mV, an ultralow I-off of 135 fA/mu m, a large I-on/I-off ratio of 8.7x 10(7) and a sub-60 mV/dec SS over 5 decade. For P-type NCFET, the non-hysteretic steep-slope switch is still reached under the synergistic effect of gate stress, defect passivation and doping engineering. The Al doping and defect passivation play the key role for reducing trap-related leakage, enhancing NC, and stabilizing multidomain switching. The highly scaled HfAlOx. CMOS NCFET shows the potential for low power logic applications.
Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs
(2014-06-01)
Lin, Chen-Wei
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Chao, Mango C. -T.
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Hsu, Chih-Chieh
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Gate oxide short (GOS) has become a common defect for advanced technologies as the gate oxide thickness of a MOSFET is greatly reduced. The behavior of a GOS-impacted MOSFET is, however, complicated and difficult to be accurately modeled at the circuit level. In this paper, we first build a golden model of a GOS-impacted MOSFET by using technology CAD, and identify the limitation and inaccuracy of the previous GOS models. Next, we propose a novel circuit-level GOS model which provides a higher accuracy of its dc characteristics than any of the previous models and being is able to represent a minimum-size GOS-impacted MOSFET. In addition, the proposed model can fit the transient characteristics of a GOS by considering the capacitance change of the GOS-impacted MOSFET, which has not been discussed in previous work. Last, we utilize our proposed GOS model to develop a novel GOS test method for SRAMs, which can effectively detect the GOS defects usually escaped from the conventional IDDQ test and March test.
Role of tungsten dopants in indium oxide thin-film transistor on radiation hardness technology
(2020-05-04)
Ruan, Dun-Bao
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Liu, Po-Tsun
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Gan, Kai-Jhih
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Chiu, Yu-Chuan
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Hsu, Chih-Chieh
The effects of radiation on tungsten doped indium oxide (IWO) thin-film transistors (TFTs) have been well investigated in this Letter. In order to achieve high stability and excellent electrical performance simultaneously even in high ionizing radiation damage ambient, different concentrations of tungsten dopant have been introduced for the TFT device fabrication. It is interesting that the high energy ionizing radiation may significantly increase the conductivity and influence the total concentration of oxygen vacancy in the transparent amorphous oxide semiconductor material, which may be completely different from the traditional radiation damage effect for silicon based CMOS devices. However, that abnormal phenomenon will be effectively suppressed by the powerful carrier suppressor, tungsten, which may have a high oxygen bond dissociation energy. Therefore, IWO devices with a 4% tungsten oxide dopant might be the optimized result even after high dosage ionizing radiation exposure. Hence, it may provide a promising radiation hardness approach to improve both the electrical characteristics and reliability for next generation displays, which can be used in the control system of nuclear power generation or space technology.