Browsing by Author "Hsu, Hsing-Hui"

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A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate
(2008-07-01)
Lin, Horng-Chih
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Hsu, Hsing-Hui
;
Su, Chun-Jung
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T-gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of single-gate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at Vd = 2 V is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.
Characteristics of poly-Si nanowire transistors with multiple-gate configurations
(2008)
Hsu, Hsing-Hui
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Lin, Homg-Chih
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Lee, Ko-Hui
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Huang, Jian-Fu
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Huang, Tiao-Yuan
Fabrication and Characterization of Multiple-Gated Poly-Si Nanowire Thin-Film Transistors and Impacts of Multiple-Gate Structures on Device Fluctuations
(2008-11-01)
Hsu, Hsing-Hui
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Liu, Ta-Wei
;
Chan, Leng
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Lin, Chuan-Ding
;
Huang, Tiao-Yuan
Several types of poly-Si nanowire (NW) thin-film transistors (TFTs) with multiple-gated (MG) configuration were demonstrated and characterized. These devices were fabricated with simple methods without resorting to costly lithographic tools and processes. The fabricated trigated devices show a low subthreshold swing (SS) of around 100 mV/dec and on/off current ratio higher than 10(8). These results clearly indicate the effectiveness of MG scheme in enhancing the device performance. Furthermore, a multiple-channel scheme was demonstrated to further increase the drive current without compromising device performance. Finally, the impact of MG on the variation of NWTFT characteristics is investigated with a clever method that allows the fabrication of test structures with identical NW channel but different gate configurations. The results,clearly show that the variation could be reduced by increasing the portion of NW channel surface that is modulated by the gate.
Impacts of Multiple-Gated Configuration on the Characteristics of Poly-Si Nanowire SONOS Devices
(2011-03-01)
Hsu, Hsing-Hui
;
Lin, Horng-Chih
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Luo, Cheng-Wei
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Su, Chun-Jung
;
Huang, Tiao-Yuan
In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, O-shaped gated OG, and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largestmemory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications.
Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices
(2011-07-01)
Luo, Cheng-Wei
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Lin, Horng-Chih
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Lee, Ko-Hui
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Chen, Wei-Chen
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Hsu, Hsing-Hui
Trap-layer-engineered poly-Si nanowire silicon-oxide-nitride-oxide-silicon (SONOS) devices with a gate-all-around (GAA) configuration were fabricated and characterized. For the first time, a clever method has been developed to flexibly incorporate Si-nanocrystal (NC) dots in different locations in the nitride layer. Three types of poly-Si GAA SONOS devices with Si-NC dots embedded in the block oxide/nitride interface, the middle of the nitride, and the nitride/tunnel oxide interface, respectively, by in situ deposition were fabricated and investigated in this paper. Our results indicate that the optimal NC location appears to be somewhere between the middle and bottom interfaces of the nitride layer.
Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors
(2009-03-01)
Lin, Horng-Chih
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Hung, Cheng-Hsiung
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Chen, Wei-Chen
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Lin, Zer-Ming
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Hsu, Hsing-Hui
In this work we report the observation and characterization of a hysteresis phenomenon in the transfer characteristics of n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Such phenomenon is observed in devices with fully depleted channel and not treated with hydrogen-related anneal. The origin of the hysteresis is identified to be related to the electron trapping and detrapping processes associated with the deep-level traps in the grain boundaries of the poly-Si channel.
Origins of Performance Enhancement in Independent Double-Gated Poly-Si Nanowire Devices
(2010-04-01)
Hsu, Hsing-Hui
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Lin, Horng-Chih
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we characterize and compare the characteristics of a poly-Si nanowire (NW) device with independent double-gated configuration under different operation modes. In the device, the tiny NW channels are surrounded by an inverted-T-shaped gate and a top gate. It is found that the device under double-gate (DG)mode exhibits significantly better performance with respect to the two single-gate (SG) modes, as indicated by a higher current drive than the combined sum of the two SG modes and a smaller subthreshold swing of less than 100 mV/dec. Origins of such improvement have been identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with the DG operation.
Performance Improvement of Polycrystalline Silicon Nanowire Thin-Film Transistors by a High-k Capping Layer
(2009-02-01)
Lee, Ko-Hui
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Hsu, Hsing-Hui
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Lin, Horng-Chih
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control. (C) 2009 The Japan Society of Applied Physics
Suspended nanochannel transistor structure and method for fabricating the same
(2010-04-22)
Lin, Horng-Chin
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Su, Chun-Jung
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Hsu, Hsing-Hui
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Li, Guan-Jang
The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered.
Threshold-Voltage Fluctuation of Double-Gated Poly-Si Nanowire Field-Effect Transistor
(2009-03-01)
Hsu, Hsing-Hui
;
Lin, Horng-Chih
;
Chan, Leng
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this letter, the fluctuation characteristics of polycrystalline silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) with independently controlled double-gate configuration were studied. The defects existing in the NW channels are identified as one of the major sources for the fluctuation. The passivation of these defects by plasma treatment is shown to be effective for reducing the fluctuation. We have also found that the fluctuation is closely related to the operation modes. When only one of the gates is employed as the driving gate to control the switching behavior of the device, an optimum bias for the other gate can be found for minimizing the fluctuation.
Tr-gate Poly-Si Thin-Film Transistor with Nanowire Channels
(2008)
Hsu, Hsing-Hui
;
Lin, Horng-Chih
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Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Tri-gated Poly-Si Nanowire SONOS Devices
(2009)
Hsu, Hsing-Hui
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Liu, Ta-Wei
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Lin, Chuan-Ding
;
Chia Kuo-Jung
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Huang, Tiao-Yuan
Si nanowire (NW) SONOS devices have recently been demonstrated as a good candidate for high-density non-volatile memory application [ 1][2]. Owing to the high surface-to-volume ratio of the NW channel, the programming and erasing (P/E) operation of the device could be performed at a lower voltage and much faster speed over the planar counterpart [2]. However, the fabrication of NW devices typically requires advanced lithographic tools and or complicated process flow. These are not compatible with the manufacturing of flat-panel products where the device feature size is generally several microns or larger. In this work, we propose a simple and cost-effective approach to integrate planar poly-Si thin-film transistors (TFTs) and tri-gated poly-Si NW SONOS devices without resorting to advanced lithographic tools. Greatly enhanced P/E speed with the use of NW structure is clearly demonstrated.
Trigated Poly-Si Nanowire SONOS Devices for Flat-Panel Applications
(2010-05-01)
Lin, Horng-Chih
;
Liu, Ta-Wei
;
Hsu, Hsing-Hui
;
Lin, Chuan-Ding
;
Huang, Tiao-Yuan
A new method is proposed and demonstrated to fabricate planar thin-film transistors and trigated nanowire (NW) devices simultaneously on the same panel. By using an oxide-nitride oxide stack as the gate dielectric, the NW devices could also serve as nonvolatile Si-oxide-nitride-oxide-Si (SONOS) memory devices. Our results indicate that the combination of trigate and NW channels help to improve the device performance in terms of steppers subthreshold swing and reduced threshold voltage. Improvement in programming and erasing efficiency of the nonvolatile SONOS memory devices is also demonstrated with the trigated NW structure.