Browsing by Author "Hsu, KC"

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A cost-effective fast frequency-hopped code-division multiple-access light source using self-seeded Fabry-Perot laser with fiber Bragg grating array
(2004-11-01)
Peng, WR
;
Peng, PC
;
Lin, WP
;
Hsu, KC
;
Lai, YC
We propose a novel light source for the optical fast frequency-hopped code-division multiple-access scheme using a self-seeded gain-switched Fabry-Perot laser diode (FP-LD) with the reconfigurable fiber Bragg grating array (FBGA). The embedded FBGA in the external cavity loop encodes the input pulses both temporally and spectrally. Before feeding back into the FP-LD, the encoded optical pulses propagate the FBGA with reverse direction and are again temporally combined. With the corporation of the variable fiber delay line, the limitation of the pulse rate by the fixed external cavity length is removed and makes the scheme more flexible. The output with sidemode suppression ratio of more than 20 dB has been obtained. With three fiber Bragg gratings on the FBGA, we demonstrate the encoded chip rate of 1.425 GHz under the driving radio frequency of 475 MHz. It is proved that a different codeword can be generated by simply reconfiguring the encoder without changing the rest of the experimental setup.
A simple dispersion measurement of fiber gratings by interferometric technique
(2006-01-01)
Sheu, LG
;
Chen, JM
;
Yu, SY
;
Hsu, KC
;
Tsai, MC
A simple dispersion measurement of fiber gratings using an un-balanced Michelson interferometer is proposed. A broadband source and an optical spectrum analyzer are used to scan the interference spectrum, and then the group time delay can be obtained rapidly by Fourier transform processing the interference spectrum. We measured the group time delays of a uniform-period FBG, a chirped FBG, an arrayed-waveguide grating interleaver, and a thin-film filter type OADM by an un-balanced Michelson and Mach-Zehnder interferometers, respectively. The experimental results excellent match the measured results of the optical network analyzer. The experimental repeatability is shown to be better than 1ps.
Characterization of porous silicate for ultra-low k dielectric application
(2002-07-01)
Liu, PT
;
Chang, TC
;
Hsu, KC
;
Tseng, TY
;
Chen, LM
Thermal stability of a porous low-k film is a critical issue for application consideration in the back-end-of-line. In this study, thermal stability of the porous silicate has been investigated by changing the thermal processing temperatures. Experimental results have shown that the dielectric constant of the porous silicate still remains below 2.0 after thermal processing at 500 degreesC for I h. A series of material analysis techniques and electrical characteristics have been used to verify the physical and chemical characteristics of the porous silicate film. (C) 2002 Elsevier Science B.V. All rights reserved.
Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
(2002)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
The turn-on mechanism of SCR device is essentially a current triggering event. While a current is applied to the base or substrate of a SCR device, it can be quickly triggered on into its latching state. In this paper, the complementary substrate-triggered SCR devices which are combined with the substrate-triggered technique and SCR devices, are first reported in the literature for using in the on-chip ESD. protection circuits. A complementary style on the substrate-triggered SCR devices is designed to discharge both of the positive and negative ESD stresses on the pad. The total holding voltage of the substrate-triggered SCR device can be increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices for the I/O pad and power pad have been successfully verified in a 0.25-mum STI CMOS process with the HBM (MM) ESD level of >8kV (650V) in a small layout area.
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
(2005)
Ker, MD
;
Chen, WY
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
A new power-rail ESD clamp circuit in a 130-nm 1-V/2.5-V CMOS process for application in 3.3-V mixed-voltage I/O interface is proposed. The devices used in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage NMOS/PMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V 1/0 interface applications. A special ESD detection circuit realized with the low-voltage devices is designed to improve ESD robustness of the stacked NMOS by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.
Down-regulation of matrix Gla protein messenger RNA in human colorectal adenocarcinomas
(2001-04-10)
Fan, CW
;
Sheu, DL
;
Fan, HA
;
Hsu, KC
;
Chang, CA
Matrix Gla protein (MGP) is a vitamin K-dependent extracellular matrix protein commonly found in a variety of tissues. In this study, we describe the potential use of MGP gene expression as the tumor marker of colorectal cancer. A decrease in expression of the MGP gene was also discovered in colorectal cancer using differential screening of cDNA libraries. The MGP expression in 80 human colorectal adenocarcinomas was quantified by a Northern blot analysis to better define the expression pattern of MGP in colorectal cancer. The expression of MGP mRNA was reduced in 63 of 80 (79%) colorectal adenocarcinomas (P < 0.001) as compared to the mRNA in adjacent normal tissue, implying that a decrease in MGP expression is associated with colorectal cancer development. The proportion of tumors with downregulated expression of MGP was lower in Duke's A/B than Duke's C/D (34 of 47 versus 26 of 33, respectively) tumors and was lower in moderate differentiation than poor differentiation (44 of 64 versus 16 of 16, respectively). However, chi (2) analysis does not reveal any correlation between a loss of MGP expression and tumor progression or differentiation state. In conclusion, the downregulation of MGP mRNA generally occurs in colorectal adenocarcinomas. Although the role of MGP in cancer development is unknown, the reduced expression of MGP may be used to distinguish the normal colorectal cells from malignant cells. (C) 2001 Elsevier Science Ireland Ltd. All rights reserved.
Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection
(2003-11-15)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
Turn-on speed is the main concern for on-chip electrostatic discharge (ESD) protection device, especially, in deep submicron complementary metal-oxide semiconductors (CMOS) processes with ultra-thin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device with substrate-triggered technique is proposed to improve the turn-on speed of SCR device for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide. From the experimental results, the switching voltage, turn-on resistance, and turn-on time of substrate-triggered SCR (STSCR) device with dummy-gate structure have been efficiently improved, as compared with the normal SCR with shallow trench isolation (STI) structure.
ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
(2002)
Ker, MD
;
Chuang, CH
;
Hsu, KC
;
Lo, WY
;
電子工程學系及電子研究所
A substrate-triggered technique is proposed to improve ESD Protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3.3V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-mum salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased similar to 65% by this substrate-triggered design.
Fiber Bragg grating sequential UV-writing method with real-time interferometric side-diffraction position monitoring
(2005-05-16)
Hsu, KC
;
Sheu, LG
;
Chuang, KP
;
Chang, SH
;
Lai, YC
This work presents a new sequential UV-writing procedure for fabricating long fiber Bragg grating (FBG) devices. To real-time accurately align the position of every exposed FBG section prior to UV exposure, a single-period reference fiber grating with strong refractive index modulation is probed by applying an interferometric side-diffraction method to measure the grating phase as the position reference. In this way the overlapped FBG sections can be connected section-by-section without obvious phase errors, even when the written index-modulation is weak. (C) 2005 Optical Society of America.
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
(2003-08-01)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V-SS and pad-to-V-DD ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-mum salicided CMOS process with the human body model (machine model) ESD level of similar to7.25 kV (500 V) in a small layout area.
Miniaturized 3-dimensional transformer design
(2005)
Chen, WZ
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
3-dimentional fully-symmetric transformers are proposed and realized in a standard CMOS technology. In contrast to their planar counterparts, the self resonant frequency (f(SR)) of the proposed architecture is improved by 26 % to 53 %, while the chip area is reduced by 40 % to 70 %. The coupling coefficient (K) can be up to 0.77 at 8 GHz in a two turn two layer architecture. Distributed capacitance model (DCM) of the 3-D transformer is also proposed f(SR) evaulation.
Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-mu m CMOS integrated circuits
(2004)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-mum CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and CDM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-mum CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.
Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process
(2005-09-01)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In order to quickly discharge the electrostatic discharge (ESD) energy and to efficiently protect the ultrathin gate oxide, a novel native-negative-channel metal oxide semiconductor (NMOS)-triggered silicon-controlled rectifier (NANSCR) is proposed for on-chip ESD protection in a 0.13-mu m complementary metal oxide semiconductor (CMOS) process with a voltage supply of 1.2 V. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger. A new whole-chip ESD protection scheme realized with the proposed NANSCR devices is also demonstrated with the consideration of pin-to-pin ESD stress. From the experimental results, the trigger voltage, holding voltage, turn-on resistance, turn-on speed, and charged-device-model (CDM) ESD level of NANSCR can be greatly improved, as compared with the traditional low-voltage-triggering SCR (LVTSCR). Under transmission line pulsing (TLP) stress, the gate leakage current of the gate monitor device protected by the proposed NANSCR is monitored after each TLP pulse, whereas the gate leakage current is not obviously increased. Therefore, the ultrathin gate oxide of the input stage can be safely protected by the new proposed NANSCR against ESD stress in the nanoscale CMOS technology.
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
(2002)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the, transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-mum CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40mumx20mum can sustain the HBM ESD stress of higher than 7kV.
Outlook for photovoltaic developments in Taiwan
(1998-05-01)
Hwang, HL
;
Hsu, KYJ
;
Lee, WI
;
Shing, YH
;
Hsu, KC
This paper describes the various aspects of photovoltaic developments ill Taiwan, which include applications of space and terrestrial solar cells, solar cell production and research on advanced thin-film solar cell materials, The advanced materials are hydrogenated polycrystalline silicon films deposited at low substrate temperatures and ternary chalcopyrite films with the potential for intrinsically stable and ultra-high-efficiency solar cells having a conversion efficiency in the vicinity of AMI 35%, (C) 1998 John Wiley & Sons, Ltd.
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
(2005-06-01)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported. Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed. The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products.
S-band gain-clamped grating-based erbium-doped fiber amplifier by forward optical feedback technique
(2006-04-03)
Yeh, CH
;
Lin, MC
;
Huang, TT
;
Hsu, KC
;
Ko, CH
An S-band gain-clamped erbium-doped fiber amplifier module, employing a fiber Bragg grating to serve as a reflected element for lasing a saturated tone injected into the module by forward optical feedback method, is proposed and investigated experimentally. Moreover, the performance and behavior of the gain and noise figure in the proposed gain- clamped S-band fiber amplifier have also been discussed in the effectively wavelength range of 1478 to 1520 nm. (c) 2006 Optical Society of America.
SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology
(2005-05-01)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Turn-on speed is the main concern for an on-chip electrostatic discharge (ESD) protection device, especially in the nanoscale CMOS processes with ultrathin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device employing a substrate-triggered technique is proposed to improve the turn-on speed of an SCR device for using in an on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible with general CMOS process, without using an extra mask layer or adding process steps. From the experimental results in a 0.25-mu m CMOS process with a gate-oxide thickness of similar to 50 angstrom, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation structure.
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
(2003-09-01)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
Turn-on efficiency is the main concern for silicon-controlled rectifier (SCR) devices used as on-chip electrostatic discharge (ESD) protection circuit, especially in deep sub-quarter-micron CMOS processes with much thinner gate oxide. A novel double-triggered technique is proposed to speed up the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide in sub-quarter-micron CMOS processes. From the experimental results, the switching voltage and turn-on time of such double-triggered SCR (DT_SCR) device has been confirmed to be significantly reduced by this double-triggered technique.
Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices
(2005)
Ker, MD
;
Chen, JH
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
A novel self-substrate-triggered (SST) technique is proposed to solve the non-uniform turn-on issue of the multi-finger GGNMOS for ESD protection. The first turned-on center finger is used to trigger on all fingers in the GGNMOS structure with self-substrate-triggered technique. So, the turn-on uniformity and ESD robustness of GGNMOS can be greatly improved by the new proposed self-substrate-triggered technique.