Browsing by Author "Hu, SF"

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A dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowire
(2004-03-01)
Hu, SF
;
Wu, YC
;
Sung, CL
;
Chang, CY
;
Huang, TY
A dual-gate-controlled single-electron transistor was fabricated by using self-aligned polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot formed by the electric field effect of the dual-gate structure was miniaturized to smaller than the state-of-the-art feature size, through a combination of electron beam lithography, oxidation, and polysilicon sidewall spacer gate formation processes. The device shows typical MOSFET I-V characteristics at room temperature. However, the Coulomb gap and Coulomb oscillations are clearly observed at 4 K.
A silicon nanowire with a Coulomb blockade effect at room temperature
(2002-05-17)
Hu, SF
;
Wong, WZ
;
Liu, SS
;
Wu, YC
;
Sung, CL
An extremely narrow and thin silicon wire has been fabricated on a silicon-on-insulator wafer (see Figure). The room-temperature Coulomb blockade effects as well as the influence of a capacitively coupled gate on the transport properties of this conducting silicon quantum wire are studied. The results obtained are encouraging for the application of such wires in single-electron transistors.
Room temperature two-terminal characteristics in silicon nanowires
(2003-02-01)
Hu, SF
;
Wong, WZ
;
Liu, SS
;
Wu, YC
;
Sung, CL
Quantum effects in silicon nanowires due to one-dimensional carrier confinement were observed at room temperature. Electrical transport properties were measured, on narrow thin-silicon-on-insulator wires that were defined by e-beam lithography and further narrowed and thinned down by oxidation to a final thickness of around 3 nm, and a width of 29 nm. The room temperature current-voltage characteristics of the resulting silicon nanowires are shown to exhibit a zero current state may be due to the occurrence of Coulomb blockade. (C) 2003 Elsevier Science Ltd. All rights reserved