Browsing by Author "Hua, CH"

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Distributed data-retention power Gating techniques for column and row co-controlled embedded SRAM
(2005)
Hua, CH
;
Cheng, TS
;
Hwang, W
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, multi-mode data-retention power gating (P.G.) techniques are presented for embedded memories. These data retention power gating techniques are applied to embedded SRAM with distributed column and row cocontrolled capabilities The SRAM array is divided into blocks. Each block has a dedicated data-retention power gating device. The data-retention power gating devices are controlled by signals from both row and column decoders. Only the selected block is powered-on. Multi-mode power gating structures proposed in this paper can provide 2X to 20X memory cell leakage reduction while maintaining good static noise margin. Simulation results show that for a 64-bit wordline, the active power reductions for 32-bit, 16-bit, and 8-bit blocks are 59%, 79%, and 94%, respectively. All the simulations and physical layout are implemented in TSMC CMOS technology.
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits
(2005)
Hua, CH
;
Hwang, W
;
Chen, CK
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional keepers. The conditional keeper is turned off at some critical moments to reduce the delay and power consumption. The timing of control signals and their effects on noise immunity, power and delay are also examined. High fan-in dynamic circuits are used to demonstrate the effectiveness of the conditional keeper on noise immunity. Distributed power gating combined with clock gating design is also examined. An the simulation results are based on TSMC 100nm CMOS technology. Compared to conventional techniques, under the same unity-gain DC noise criteria, more than 20% power reduction and 20% delay reduction are achieved. Under the same delay criteria, more than 1.25X noise immunity improvement is attained.