Distributed data-retention power Gating techniques for column and row co-controlled embedded SRAM

Abstract

In this paper, multi-mode data-retention power gating (P.G.) techniques are presented for embedded memories. These data retention power gating techniques are applied to embedded SRAM with distributed column and row cocontrolled capabilities The SRAM array is divided into blocks. Each block has a dedicated data-retention power gating device. The data-retention power gating devices are controlled by signals from both row and column decoders. Only the selected block is powered-on. Multi-mode power gating structures proposed in this paper can provide 2X to 20X memory cell leakage reduction while maintaining good static noise margin. Simulation results show that for a 64-bit wordline, the active power reductions for 32-bit, 16-bit, and 8-bit blocks are 59%, 79%, and 94%, respectively. All the simulations and physical layout are implemented in TSMC CMOS technology.