Browsing by Author "Huang, Hsuan-Ming"

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A Unified Parameterization Technique for TFT-LCD Panel Design Optimization
(2009)
Huang, Hsuan-Ming
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Li, Yiming
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電信工程研究所
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Institute of Communications Engineering
Display is the most power-hungry component in electronics industry. Power-efficient design is strongly required in thin film transistor liquid-crystal display (TFT-LCD) portable products. This work proposes a unified parameterization technique for modeling and multi-objective optimization of TFT-LCD panel using a two-stage response surface model (RSM) and genetic algorithm (GA). To achieve designing specification in circuit and system levels with minimal power consumption simultaneously, a power-delay product is considered as the object function of the TFT-LCD panel optimization. Simulation-validated RSMs and GA are thus implemented into a unified optimization framework for the design optimization problem. Comparing with the conventional design flow using CAD tools, a 21.5% reduction in the power-delay of TFT-LCD panel is achieved with 95% accuracy. Moreover, the time required for the optimization process is significantly reduced by 288 times. We notice that the proposed unified parameterization technique is object flexible and can further optimize the multi-objective system performances (i.e. crosstalk, leakage current, brightness, etc.). The unified parameterization framework may benefit the high performance display panel design in the photonics industry.
Characteristic fluctuation dependence on discrete dopant for 16nm SOI FinFETs at different temperature
(2007)
Li, Yiming
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Hwang, Chih-Hong
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Yu, Shao-Ming
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Huang, Hsuan-Ming
;
Yeh, Ta-Ching
In this paper, we numerically study the discrete-dopant-induced characteristic fluctuations in 16nnn silicon-on-insulator (SOI) FinFETs. For devices under different temperature condition, discrete dopants are statistically generated and positioned into the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Electrical characteristics' fluctuations are growing worse when the substrate temperature increases, the standard deviation of threshold voltage increases 1.75 times when substrate temperature increases from 300K to 400K for example. This "atomistic" device simulation technique is computationally cost-effective and provides us an insight into the problem of discrete-dopant-induced fluctuation and the relation between the fluctuation and thermal effect.
Comprehensive Examination of Threshold Voltage Fluctuations in Nanoscale Planar MOSFET and Bulk FinFET Devices
(2008)
Hwang, Chih-Hong
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Cheng, Hui-Wen
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Yeh, Ta-Ching
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Li, Tien-Yeh
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Huang, Hsuan-Ming
Intrinsic fluctuations on device characteristics, such as the threshold voltage (V(th)) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced Vth fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO(2) for the 1.2 and 0.8 nm EOTs, Al(2)O(3) for the 0.4 nm EOT and HfO(2) for the 0.2 nm EOT) are then for the first time compared with the results of 16nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property. Result of this study confirms the suppression of Vth fluctuations with the gate oxide thickness scaling (using high-kappa dielectric). It's found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device's scaling and have potential in the nanoelectronics application.
Computational Statistics Approach to Capacitance Sensitivity Analysis and Gate Delay Time Minimization of TFT-LCDs
(2010)
Li, Yiming
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Huang, Hsuan-Ming
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電信工程研究所
;
Institute of Communications Engineering
In this paper, we practically implement a systematical method for thin-film transistor liquid-crystal display (TFT-LCD) design optimization and sensitivity analysis. Based upon a three-dimensional (3D) field solver and a Design of Experiments, we construct a second-order response surface model (RSM) to examine the capacitances' effect on the performance of an interested TFT-LCD pixel. The constructed RSMs are reduced using a step-wise regression. We verify the accuracy using the normal residual plots and their residual of squares. According to the models, we then analyze the sensitivity of the capacitances by considering the design parameters as changing factors (i.e., the size variation and the position shift) under an assumption of Gaussian distribution. Consequently, we further apply the models to optimize the designed circuit. The designing parameters of these models are selected and optimized to fit the designing target of the examined circuit by the genetic algorithm in our unified optimization framework. This computational statistics method predicts the capacitances' effects on the gate delay time and compares with full 3D simulation approaches, it shows the engineering practicability in display panel industry.
Discrete Dopant Induced Characteristic Fluctuations in 16nm Multiple-Gate SOI Devices
(2007)
Li, Yiming
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Hwang, Chih-Hong
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Huang, Hsuan-Ming
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Yeh, Ta-Ching
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電信工程研究所
Discrete Dopant Induced Electrical and Thermal Fluctuation in Nanoscale SOI FinFET
(2007)
Li, Yiming
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Hwang, Chih-Hong
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Yu, Shao-Ming
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Huang, Hsuan-Ming
;
電信工程研究所
The International Roadmap for Semiconductors has forecasted a transition from conventional bulk device to silicon-on-insulator (SOI) one, and then to multiple-gate SOI for high-performance devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, the discrete dopant induced electrical and thermal fluctuation of 16nm SOI FinFETs is for the first time explored. A three-dimensional atomistic" device simulation with quantum hydrodynamic equation is proposed and performed for electrical and thermal characteristics of the discrete dopant fluctuated SOI FinFETs. Discrete dopants are statistically positioned in the 3D channel region to study associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Effect of the discrete-dopant-number- and discrete-dopant-position-induced fluctuations on device characteristic including variations of the lattice and electron temperatures are advanced. The large-scale computational statistics study provides us an insight into the fluctuation of electrical and thermal characteristics and mechanism of immunity against fluctuation in SOI FinFETs.
Fast-Yet-Accurate Statistical Soft-Error-Rate Analysis Considering Full-Spectrum Charge Collection
(2013-03-01)
Huang, Hsuan-Ming
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Wen, Charles H. -P.
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交大名義發表
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傳播研究所
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電機資訊學士班
Large-scale "atomistic" approach to discrete-dopant-induced characteristic fluctuations in silicon nanowire transistors
(2008-06-01)
Li, Yiming
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Hwang, Chih-Hong
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Huang, Hsuan-Ming
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電信工程研究所
;
Institute of Communications Engineering
Nanowire fin-typed field effect transistors (FinFETs) are ultimate structures and potential candidates for next generation nanoelectronic devices. Due to the limitation of manufacturability, nanowire transistors with a perfect gate structure (i.e., a surrounding gate with 100% gate-coverage ratio) theoretically are not always guaranteed. Impact of the discrete dopants on device performance is crucial in determining the behaviour of nanoscale semiconductor devices. The immunity of nanowire transistor against random discrete-dopant-induced fluctuation may suffer from the variation of gate-coverage-ratio. Therefore, in this paper, we for the fist time study the impact of non-ideal gate coverage on immunity against random-dopant-induced fluctuations for nanowire FinFETs. A 3D statistically sound "atomistic" approach for analyzing random-dopant effect in nanodevice is presented. Discrete dopants are statistically positioned into the channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Our results confirm that the influence of non-ideal gate coverage disturbs the,channel controllability of nanowire FinFETs and thus decreases the immunity against discrete-dopant-induced fluctuation. This study provides an insight into them problem of fluctuation in nanowire transistors and,shows the importance of gate-coverage ratio on device's immunity against discrete-dopant-induced fluctuation. (C) 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults-From Device to Circuit Level
(2016-04)
Huang, Hsuan-Ming
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Wen, Charles H. -P.
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電機學院
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College of Electrical and Computer Engineering
This paper investigated the soft errors caused by particle strikes, such as high-energy neutrons, extending beyond the deep submicrometer era. Considering the structure of the layout and resulting nuclear reactions, multiple transient faults (MTFs) tend to be induced more frequently than do single transient faults (STFs), due to the effects of technology scaling. This means that the soft error rates (SER) are beyond traditional netlist-based STF analysis, which can result in serious mis-estimations. This paper proposes a layout-based soft error estimation framework, which takes into account MTFs from the device level to the circuit level. This framework comprises two systems: 1) generation and 2) propagation. In the generation system, transient faults are modeled through nuclear reactions, charge collection, and voltage transformation at the device level. The propagation system abstracts these effects from the device level to the circuit level, taking into account three masking mechanisms associated with the propagation of transient faults. Experiment results demonstrate that the SER can be underestimated by an average of 15.72% if only single (rather than multiple) transient faults are taken into account. Our results indicate that netlist-based analysis for the estimation of SERs is no longer sufficient, due to the overwhelming influence of the structural layout. Thus, using benchmark c432, a tighter layout will result in an SER 34% higher than that generated in a looser layout.
Parameterized Display Performances Behavioral Modeling and Optimization for TFT-LCD Panel
(2009)
Huang, Hsuan-Ming
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, we implement a systematical method for thin film transistor liquid-crystal display (TFT-LCD) design optimization and sensitivity analysis. Based upon a three-dimensional (3D) field solver, Simulation Program with Integrated Circuit Emphasis (SPICE), and a Design of Experiments, we construct a second-order response surface model (RSM) for the performances of an interested TFT-LCD panel. The constructed RSMs are reduced using a step-wise regression. The adequacy and accuracy using the normal residual plots and their residual of squares are verified. According to the constructed models, we then analyze the sensitivity of the performances by considering the design parameters as changing factors (i.e., the size variation, position shift and driving setting) under an assumption of Gaussian distribution. We also could apply the models to optimize the designed circuit. The designing parameters of these models are selected and optimized to fit the designing target of the examined circuit by the genetic algorithm in our unified optimization framework. This computational statistics method can predict the TFT-LCD performances and show the engineering practicability in display panel industry.
Reduction of Discrete-Dopant-Induced High-Frequency Characteristic Fluctuations in Nanoscale CMOS Circuit
(2008)
Li, Yiming
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Hwang, Chih-Hong
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Yeh, Ta-Ching
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Huang, Hsuan-Ming
;
Li, Tien-Yeh
As the dimension of semiconductor device shrunk into nanoscale, characteristic fluctuation is more pronounced, and become crucial for circuit design. Diverse approaches have been reported to investigate and suppress the random-dopant-induced fluctuations in devices. However, attention is seldom drawn to the existence of high-frequency characteristic fluctuations of active device. In this paper, intrinsic high-frequency characteristic fluctuations of the nanoscale MOSFET circuit induced by random dopants are intensively explored using an experimentally validated simulation methodology, where fluctuation suppression technique is further examined. The circuit gain, the 3db bandwidth and the unity-gain bandwidth of the tested circuit are estimated concurrently capturing the discrete-dopant-number-and discrete-dopant-position-induced fluctuations. This study provides an insight into discrete-dopant-induced intrinsic high-frequency characteristic fluctuations and examines the potential fluctuation suppression technique for nanoscale transistor circuit.
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
(2012-01-01)
Peng, Huan-Kai
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Huang, Hsuan-Ming
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Kuo, Yu-Hsin
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Wen, Charles H. -P.
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電機工程學系
This article re-examines the soft error effect caused by radiation-induced particles beyond the deep submicron regime. Considering the impact of process variations, voltage pulse widths of transient faults are found no longer monotonically diminishing after propagation, as they were formerly. As a result, the soft error rates in scaled electronic designs escape traditional static analysis and are seriously underestimated. In this article we formulate the statistical soft error rate (SSER) problem and present two frameworks to cope with the aforementioned sophisticated issues. The table-lookup framework captures the change of transient-fault distributions implicitly by using a Monte-Carlo approach, whereas the SVR-learning framework does the task explicitly by using statistical learning theory. Experimental results show that both frameworks can more accurately estimate SERs than static approaches do. Meanwhile, the SVR-learning framework outperforms the table-lookup framework in both SER accuracy and runtime.
Three-dimensional simulation of random-dopant-induced threshold voltage fluctuation in nanoscale Fin-typed field effect transistors
(2007)
Li, Yiming
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Hwang, Chih-Hong
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Yu, Shao-Ming
;
Huang, Hsuan-Ming
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資訊工程學系
Nanoscale multiple-gate fin-typed field effect transistors (FinFETs) are promising candidates for next generation semiconductor devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, we study the discrete-dopant-induced potential and threshold voltage fluctuations in 16nm triple-gate FinFET devices. Discrete dopants are statistically positioned into the three dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". It is found that the inhomogeneity of the potential induced by the discreteness of the channel dopants significantly disturbs device threshold voltage, and thus the device characteristics. This study provides an insight into the source of fluctuation and fluctuations induced by discrete dopants in ultra-small field effect transistors with vertical channel structures.