Browsing by Author "Huang, Wen-Hsien"

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3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400 degrees C Sequential Layered Integration
(2012-01-01)
Lien, Yu-Chung
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Hsieh, Wei-Shang
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Tu, Cheng-Hui
For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm(2)/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400 degrees C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed dat-storage application era.
A sandwiched buffer layer enabling pulsed ultraviolet- and visible-laser annealings for direct fabricating poly-Si field-effect transistors on the polyimide
(2017-07-10)
Kao, Ming-Hsuan
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Huang, Wen-Hsien
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Shieh, Jia-Min
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Shen, Chang-Hong
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Lee, Pei-Kang
A sandwiched buffer layer of SiO2/Al/SiO2 enables ultraviolet-laser crystallization and visible-laser activation for direct fabrication of a poly-Si flexible field-effect-transistor (fFET) on polyimides. The buffer layer can produce heat accumulation and laser reflection from the Al/SiO2 interface to facilitate grain growth and contact resistance reduction of poly-Si without damaging the polyimide substrate. The feature size of poly-Si fFET has shrunk to 400nm via laser annealing, with the on/off current-ratio exceeding 5 x 10(6) and a subthreshold swing of 190 mV/dec. Moreover, the transfer characteristics of fFET by tension stress can be maintained until the bending radius reaches over 15 mm. Published by AIP Publishing.
Charge-trap non-volatile memories fabricated by laser-enabled low-thermal budget processes
(2015-11-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Pan, Fu-Ming
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Yang, Chih-Chao
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Shen, Chang-Hong
We fabricated charge-trap non-volatile memories (NVMs) using low thermal budget processes, including laser-crystallization of poly-Si thin film, chemical vapor deposition deposition of a stacked memory layer, and far-infrared-laser dopant activation. The thin poly-Si channel has a low defect-density at the interface with the bulk, resulting in a steep subthreshold swing for the NVM transistors. The introduction of the stacked SiO2/AlOxNy tunnel layer and the SiNx charge-trap layer with a gradient bandgap leads to reliable retention and endurance at low voltage for the NVMs. The low thermal budget processes are desirable for the integration of the nano-scaled NVMs into system on panels. (C) 2015 AIP Publishing LLC.
CO2 laser annealing of low-hole-concentration polycrystalline germanium for the fabrication of enhancement-mode nMOSFET
(2018-10-01)
Kasirajan, Han Anand
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Huang, Wen-Hsien
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Kao, Ming-Hsuan
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Wang, Hsing-Hsiang
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Shieh, Jia-Min
A p-type polycrystalline Ge (poly-Ge) film processed by UV and CO2 laser annealing reduces the hole concentration from 6 x 10(18) to 2 x 10(16) cm(-3), accompanied by poly-grain growth. The decrease in hole concentration arises from the defect annealing using a CO2 laser, as demonstrated by the changes in the work function, that is, the valence-band maximum (VBM). The laser processes reduce the thermal budget for the fabrication of an enhancement-mode poly-Ge nMOSFET, which has a l(on)/l(off) ratio of 5 x 10(3), a Vth of 2V, and a subthreshold swing of 250 mV/dec., and will be potential fabrication methods for monolithic 3D integrated circuits in the future. (C) 2018 The Japan Society of Applied Physics
Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability
(2013-11-11)
Chiou, Uio-Pu
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Shieh, Jia-Min
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Yang, Chih-Chao
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Huang, Wen-Hsien
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Kao, Yo-Tsung
We fabricated nano-crystalline Si (nc-Si: H) thin-film transistors (TFTs) with a double-metal-gate structure, which showed a high electron-mobility (mu(FE)) and adjustable threshold voltages (V-th). The nc-Si: H channel and source/drain (S/D) of the multilayered TFT were deposited at 375 degrees C by inductively coupled plasma chemical vapor deposition. The low grain-boundary defect density of the channel layer is responsible for the high mu(FE) of 370 cm(2) /V-s, a steep subthreshold slope of 90 mV/decade, and a low V-th of -0.64 V. When biased with the double-gate driving mode, the device shows a tunable V-th value extending from -1V up to 2.7 V. (C) 2013 AIP Publishing LLC.
Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing
(2017-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Kao, Ming-Hsuan
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Shen, Chang-Hong
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Huang, Tzu-En
A low-thermal-budget n-type polycrystalline Ge (poly-Ge) channel that was prepared by plasma in-situ-doped nanocrystalline Ge (nc-Ge) and visible pulsed laser annealing exhibits a high electrically active concentration of 2 x 10(19) cm(-3) and a narrow Raman FWHM of 3.9 cm(-1). Furthermore, the fabricated n-type poly-Ge junctionless FinFET (JL-FinFET) shows an I-on/I-off ratio of 6 x 10(4), V-th of % -0.3 V, and a subthreshold swing of 237mV/dec at V-d of 1V and DIBL of 101mV/V. The poly-Ge JL-FinFET with a high-aspect-ratio fin channel is less sensitive to V-th roll-off and subthreshold-swing degradation as the gate length is scaled down to 50 nm. This low-thermal-budget JL-FinFET can be integrated into three-dimensional sequential-layer integration and flexible electronics. (C) 2017 The Japan Society of Applied Physics
Fabrication and characterization of three-dimensional all metallic photonic crystals for near infrared applications
(2009-01-26)
Yang, Yu-Lin
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Hou, Fu-Ju
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Wu, Shich-Chuan
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Huang, Wen-Hsien
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Lai, Ming-Chih
Three-dimensional all metallic photonic crystals with a feature size of 0.20 mu m were fabricated using electron-beam lithography with the photoresist of hydrogen silesquioxane. This process method has high compatibility with the fabrication of damascene copper interconnections and also simplifies the whole process flow. The dependence of the complete photonic band gaps on polarization was experimentally observed and compared with the simulation results. The band edge for the four-layer lattice was found at a wavelength of around 0.80 mu m in normal incidence.
Fabrication and properties of Cu-Ni mixed-metal periodical array for midinfrared filtering and hydrophobic application
(2008-09-01)
Huang, Wen-Hsien
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Yang, Yu-Lin
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Wu, Shich-Chuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Cu was grown successfully on Ni film as a conductive layer that demonstrated a stronger Cu (111) preferred crystallographic orientation. Furthermore, we studied the scale effect of various periods of patterned Ni lines separated by variable widths of SiO2. When Cu was electroplated onto this patterned Ni, it preferentially deposited on the Ni edges adjacent to the SiO2 stripes, resulting in a Cu-Ni-Cu-SiO2, Cu-SiO2-Cu, or Cu-Cu structure, depending on the dimensions of the starting Ni pattern and the deposition time. There are two reflective dips at 2.2 and 8 mu m wavelengths using Fourier transform infrared spectroscopy, which revealed a trend of narrower bandwidth in reflective spectra and a redshift effect with increasing deposition time. Interestingly, a hydrophobic surface was also observed due to its particular surface-roughness structures that could be controlled by the deposition time and altered the contact angle from 72 degrees to 110 degrees without coating any extra low free-energy materials. (C) 2008 American Vacuum Society.
Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing
(2012-04-02)
Lien, Yu-Chung
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Tu, Cheng-Hui
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Wang, Chieh
The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/erase speed of 1 mu s under low operating voltages of +/-7V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3700729]
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
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Shen, Chang-Hong
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Shieh, Jia-Min
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Li, Kai-Shin
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Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester
(2014)
Shen, Chang-Hong
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Chen, Chien-Fu
For the first time, we report heterogeneously integrated sub-40nm epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits and efficient photovoltaic energy harvester. Threshold voltage engineering and driving current boosting technologies enable stackable Ge/Si UTB (< 15nm) MOSFETs, CMOS inverter and SRAM (SNM=270mV@0.7V) achieve low operation voltage. Stackable 1-T NVM with high speed (100ns) and low driving-voltage operation provide power-off storage while SRAM serve as power-on working memory. 100% aperture ratio SiGeC ambient light energy harvester with maximum output power of 7mW/cm(2) layered on the monolithic 3D-IC chip envisions a self-powered monolithic 3D-IC technology for advanced low-power wire-less sensor networks, wearable devices, and devices for Internet of Things.
High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
(2017-05-02)
Wu, Tsung-Ta
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Huang, Wen-Hsien
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Yang, Chih-Chao
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Chen, Hung-Chun
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Hsieh, Tung-Ying
Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (I-on)/subthreshold swing (S.S.) of 181 mu A/mu m/107 mV/dec and 188 mu A/mu m/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at V-DD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
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Cho, Ta-Chun
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Sung, Po-Jung
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Kao, Kuo-Hsing
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Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
High-Performance Germanium Thin-Film Transistors With Single-Crystal-Like Channel via Continuous-Wave Laser Crystallization
(2018-12-01)
Li, Yi-Shao
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Wu, Chun-Yi
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Liao, Chan-Yu
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Huang, Wen-Hsien
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Shieh, Jia-Min
This letter reports of the fabrication of high-performance p-channel polycrystalline germanium (poly-Ge) thin-film transistors (TFTs) using continuous-wave laser crystallization (CLC). During the CLC process, the direction of crystallization matches the direction of laser scanning due to a strong temperature gradient in the melting region. This makes it possible to fabricate high-quality poly-Ge thin films with 1-D longitudinal grains as large as 2 mu m x 20 mu m. We fabricated the proposed p-channel CLC Ge TFTs with channel width of 0.7 mu m and a channel length each of 0.7 mu m. Consequently, the proposed p-channel CLC Ge TFTs with single-crystal-like channel fabricated on a longitudinal grain with biaxial tensile strain achieved a superior field-effect mobility of 1014.9 cm(2/)V-s.
High-performance n-channel polycrystalline germanium thin-film transistors via continuous-wave laser crystallization and green nanosecond laser annealing for source and drain dopant activation
(2019-06-01)
Li, Yi-Shao
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Liang, Hao-Hsiang
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Wu, Chun-Yi
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Huang, Wen-Hsien
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Luo, Jun-Dao
High-quality polycrystalline germanium (poly-Ge) films have been successfully fabricated via the continuous-wave laser crystallization (CLC) process. Grain sizes as large as 0.8 mu m were obtained for the poly-Ge films by CLC at 5.7 W. Furthermore, the source and drain dopants could then be effectively activated by green nanosecond laser annealing (GNS-LA). Consequently, n-channel CLC Ge thin-film transistors (TFTs) with a high field-effect mobility of 576 cm(2) V-1 s(-1) were demonstrated for an effective channel width of 0.86 mu m and a channel length of 0.5 mu m. It is shown that CLC combined with GNS-LA is effective for attaining high-performance n-channel poly-Ge TFTs. (c) 2019 The Japan Society of Applied Physics
High-performance p-channel thin-film transistors with lightly doped n-type excimer-laser-crystallized germanium films
(2017-06-01)
Liao, Chan-Yu
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Huang, Ching-Yu
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Huang, Ming-Hui
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Huang, Wen-Hsien
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Shen, Chang-Hong
High-performance polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) fabricated with lightly doped Ge thin films by excimer laser crystallization (ELC) and counter doping (CD) have been demonstrated. High-quality n-type Ge thin films with a grain size as large as 1 mu m were fabricated by ELC in the super lateral-growth regime and CD at a dose of 1 x 10(13) cm(-2) or higher. Consequently, a superior field-effect mobility of 271cm(2)V(-1)s(-1) and a high on/off current ratio of 2.7 x 10(3) have been obtained for p-channel Ge TFTs with the channel width and length of both 0.5 mu m fabricated by ELC at 300mJ/cm(2) and CD at a dose of 1 x 10(13)cm(-2). The effects of ELC conditions and CD dose on the electrical characteristics of p-channel Ge TFTs were also investigated. (C) 2017 The Japan Society of Applied Physics.
High-Performance Recessed-Channel Germanium Thin-Film Transistors via Excimer Laser Crystallization
(2018-03-01)
Liao, Chan-Yu
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Chen, Shih-Hung
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Huang, Wen-Hsien
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Shen, Chang-Hong
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Shieh, Jia-Min
This letter demonstrates the excimer laser crystallization (ELC) of germanium (Ge) thin films with the recessed-channel (RC) structure for high-performance p-channel Ge thin-film transistors (TFTs). Using ELC, large longitudinal grainswith a single perpendicular grain boundary (GB) in the center of the recessed region were formed. This can be attributed to the lateral grain growth from unmelted Ge solid seeds in the thick region toward the complete melting recessed region during ELC. Consequently, the proposed p-channel RC-ELC Ge TFTs possessing large longitudinal grains without the perpendicular GB in the channel region exhibited a superior field-effect holemobility of 447 cm(2)V(-1)s(-1) with minor performance deviation.
Investigation of Characteristics of Multi-Function ZnO Thin Film Deposited With Various Argon and Oxygen Ratios
(2009)
Hsu, Che-Wei
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Cheng, Tsung-Chieh
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Yang, Chun-Hui
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Shen, Yi-Ling
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Wu, Jong-Shin
The ZnO thin film was deposited on a glass substrate at RT by the RF reactive magnetron sputtering method. Structural, chemical, optical, and hydrophilic/hydrophobic properties are measured by using a surface profilometer, an x-ray diffractometry (XRD), an x-ray photoelectron spectroscopy (XPS), a UV-VIS spectrophotometer, and a contact angle system, respectively. Results show that the deposition rate decreases with increasing O(2)/(Ar+O(2)) ratio. In additiion, the best stoichiometric and quality of ZnO thin film was observed at 0.30 Of O(2)/(Ar+O(2)) ratio, which shows the smallest FWHM and the strongest O-Zn strength. Regardless Of O(2)/(Ar+O(2)) ratio effect or thickness effect, high transmittance (> 86%) in the visible region is observed, while the UV-shielding characteristics depend upon both the magnitude of film thickness. The film thickness plays a more prominent role in controlling optical properties, especially in the UV-shielding characteristics, than the O(2)/(Ar+O(2)) ratio. However, the hydrophobic characteristics can be obtained when the glass coating with ZnO thin films. In general, with properly coated ZnO thin film, we can obtain a glass substrate which is highly transparent in the visible region, has good UV-shielding characteristics, and possesses highly hydrophobic characteristics (self-clean capability), which is highly suitable for applications in the glass industries.
Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes
(2016-06-13)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Shen, Chang-Hong
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Huang, Tzu-En
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Wang, Hsing-Hsiang
A doping-free poly-Ge film as channel material was implemented by CVD-deposited nano-crystalline Ge and visible-light laser crystallization, which behaves as a p-type semiconductor, exhibiting holes concentration of 1.8 x 10(18) cm(-3) and high crystallinity (Raman FWHM similar to 4.54 cm(-1)). The fabricated junctionless 7 nm-poly-Ge FinFET performs at an I-on/I-off ratio over 10(5) and drain-induced barrier lowering of 168mV/ V. Moreover, the fast programming speed of 100 mu s-1 ms and reliable retention can be obtained from the junctionless poly-Ge nonvolatile-memory. Such junctionless poly-Ge devices with low thermal budget are compatible with the conventional CMOS technology and are favorable for 3D sequential-layer integration and flexible electronics. Published by AIP Publishing.
Layer-by-Layer Copper Photonic Crystals for Near Infrared Spectral Region
(2010)
Wu, Shich-Chuan
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Yang, Yu-Lin
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Huang, Wen-Hsien
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Huang, Yang-Tung
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電子工程學系及電子研究所
We selected copper as the material to form the 3D structures with feature sizes of 0.4 mu m to study its desirable optical properties at near infrared wavelengths from using the high compatible process of damascene copper interconnections technique. The reflectance and transmittance spectra of the 3D copper photonic crystals were measured with the Fourier-transform infrared (FTIR) spectroscopy and simulated with the 3D FDTD method. Through both the experimental observation and the calculation verification, the characterization of the PBG is right at near infrared wavelengths. It is worth noted that some interesting behavior were observed in the spectra and transmitting ratio under different polarization incident conditions.