Browsing by Author "Huang, Ya-Shih"

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A multicycle communication architecture and synthesis flow for global interconnect resource sharing
(2008)
Huang, Wei-Sheng
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Hong, Yu-Ru
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Huang, Juinn-Dar
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Huang, Ya-Shih
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電子工程學系及電子研究所
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distributed register (DR) architecture to cope with this increasing latency. The DR architecture, though allows multicycle communication, introduces extra overhead on interconnect resource. In this paper, we propose the Regular Distributed Register - Global Resource Sharing (RDR-GRS) architecture to enable global sharing of interconnects and registers. Based on the RDR-GRS architecture, we further define the channel and register allocation problem as a path scheduling problem of data transfers. A formal and flexible formulation of this problem is then presented and optimally solved by Integer Linear Programming (ILP). Experimental results show that RDR-GRS/ILP can averagely reduce 58% wires and 35% registers compared to the previous work.
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
(2009-12-01)
Huang, Ya-Shih
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Hong, Yu-Ju
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Huang, Juinn-Dar
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle Communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It Features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.
Layer-Aware Design Partitioning for Vertical Interconnect Minimization
(2011)
Huang, Ya-Shih
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Liu, Yang-Hsiang
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Huang, Juinn-Dar
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Three-dimensional (3D) design technology, which has potential to significantly improve design performance and ease heterogeneous system integration, has been extensively discussed in recent years. This emerging technology allows stacking multiple layers of dies and typically resolves the vertical inter-layer connection issue by through-silicon vias (TSVs). However, TSVs also occupy significant silicon estate as well as incur reliability problems. Therefore, the deployment of TSVs must be very judicious in 3D designs. In this paper, we propose an iterative layer-aware partitioning algorithm, named iLap, for TSV minimization in 3D structures. iLap iteratively applies multi-way min-cut partitioning to gradually divide a given design layer by layer in the bottom-up fashion. Meanwhile, iLap also properly fulfills a specific I/O pad constraint incurred by 3D structures to further improve its outcome. Experimental results show that iLap can reduce the number of TSVs by about 35% as compared to several existing state-of-the-art methods. We believe a good TSV-minimized 3D partitioning solution can serve as a good starting point for further tradeoff operations between TSV count and wirelength.
Simultaneous Data Transfer Routing and Scheduling for Interconnect Minimization in Multicycle Communication Architecture
(2009)
Hong, Yu-Ju
;
Huang, Ya-Shih
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In deep submicron technology, wire delay is no longer negligible and is gradually becoming a dominant factor of system performance. Several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this paper, we formulate channel and register allocation within a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for minimizing global interconnect resources. We also present an innovative algorithm with both spatial and temporal considerations. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.
Thermal-Aware Logic Block Placement for 3D FPGAs Considering Lateral Heat Dissipation
(2012)
Huang, Juinn-Dar
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Huang, Ya-Shih
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Hsu, Mi-Yu
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Chang, Han-Yuan
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交大名義發表
TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance
(2015-08-01)
Huang, Ya-Shih
;
Chang, Han-Yuan
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The emerging three-dimensional (3D) technology is considered as a promising solution for achieving better performance and easier heterogeneous integration. However, the thermal issue becomes exacerbated primarily due to larger power density and longer heat dissipation paths. The thermal issue would also be critical once FPGAs step into the 3D arena. In this article, we first construct a fine-grained thermal resistive model for 3D FPGAs. We show that merely reducing the total power consumption and/or minimizing the power density in vertical direction is not enough for a thermal-aware 3D FPGA backend (placement and routing) flow. Then, we propose our thermal-aware backend flow named TherWare considering location-based heat balance. In the placement stage, TherWare not only considers power distribution of logic tiles in both lateral and vertical directions but also minimizes the interconnect power. In the routing stage, TherWare concentrates on overall power minimization and evenness of power distribution at the same time. Experimental results show that TherWare can significantly reduce the maximum temperature, the maximum temperature gradient, and the temperature deviation only at the cost of a minor increase in delay and runtime as compared with present arts.