Browsing by Author "Hwang"

Now showing 1 - 10 of 10

Asynchronous first-in-first-out cell
(2007-08-21)
Chu
;
Yeh-Lin
;
Hwang
;
Wei
The present invention discloses an asynchronous first-in-first-out cell, wherein modified Muller C elements are used to reduce the complexity of the circuit of the asynchronous first-in-first-out cell; the asynchronous first-in-first-out cell of the present invention not only can be reusable, but also can apply to a single-supply-voltage system with a single clock frequency or multiple clock frequencies and a multiple-supply-voltage system with a single clock frequency or multiple clock frequencies. Further, when the asynchronous first-in-first-out cell of the present invention is applied to the interface circuit of a dual-supply-voltage 16-point radix-22GALS-based FFT architecture, considerable power saving and latency reduction can be achieved.
Butterfly match-line structure and search method implemented thereby
(2011-03-08)
Huang
;
Po-Tsang
;
Hwang
;
Wei
;
Chang
The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.
Clock switching circuit
(2007-08-21)
Wu
;
Jian-Hua
;
Hwang
;
Wei
The present invention discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs.
Iris recognition method utilizing matching pursuit algorithm
(2011-04-05)
Che
;
Wen-Gang
;
Lin
;
Jian-Liang
;
Hwang
The present invention disclose an iris recognition method, which utilizes a matching pursuit algorithm to simplify the extraction and reconstruction of iris features and reduce the memory space required by each iris feature vector without the penalty of recognition accuracy. The iris recognition method of the present invention comprises an iris-localization component and a pattern matching component. The iris-localization component locates the iris region via the color difference between different portions of the eyeball. The primary iris features are extracted from iris information and transformed into a sequence of iris feature vectors by a matching pursuit algorithm. Thus, the iris image can be represented by a sequence of atoms, and each atom contains base, amplitude and location. Then, the comparison between the feature vectors of two irises is performed to determine whether the two irises match.
Leakage current cut-off device for ternary content addressable memory
(2010-06-15)
Huang
;
Po-Tsang
;
Liu
;
Wen-Yen
;
Hwang
A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode.
Pipeline-based reconfigurable mixed-radix FFT processor
(2010-12-07)
Lai
;
Chi-Chen
;
Hwang
;
Wei
The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.
Power gating structure having data retention and intermediate modes
(2007-03-13)
Hua
;
Chung-Hsien
;
Hwang
;
Wei
The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.
Stored don't-care based hierarchical search-line scheme
(2009-04-28)
Chang
;
Shu-Wei
;
Hwang
;
Wei
;
Chang
In the proposed stored don't-care hierarchical search-line scheme, a content-addressable memory (CAM) is divided into several blocks. Each block contains a plurality of local search-lines, a global search-line, a buffer and a memory memory cell. Data are stored in the blocks in order according to the length of the prefix. Data with the longest prefix is stored at the bottommost, and its don't-care state is used as the control signal of the buffer to control whether to transfer the data on the global search-line to the local search-line or not. The local search-line then transfer the value into the memory cell. There is no complex control circuit and extra storage device needed. Moreover, because the control signal directly comes from the don't-care state, power consumption on search-lines can be effectively reduced with no increase of search delay.
Super leakage current cut-off device for ternary content addressable memory
(2009-11-10)
Huang
;
Po-Tsang
;
Liu
;
Wen-Yen
;
Hwang
A super leakage current cut-off device for a ternary content addressable memory (TCAM) is provided. For various operations of the TCAM, the device uses the high-end and low-end power gating control transistors to turn on/off the don't-care cells to reduce the leakage current passing through the don't-care cells.
XOR-based conditional keeper and an architecture implementing its application to match lines
(2008-04-15)
Hua
;
Chung-Hsien
;
Peng
;
Chi-Wei
;
Hwang
The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed. Further, the XOR-based conditional keeper of the present invention can also apply to all kinds of dynamic circuits, particularly to a high fan-in circuit.