Browsing by Author "Hwang, Chih-Hong"

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Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants
(2010-04-01)
Lee, Kuo-Fu
;
Li, Yiming
;
Hwang, Chih-Hong
;
傳播研究所
;
電機工程學系
Characteristic variability of a transistor is a crucial issue for nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, we explore the asymmetric sketch of the random dopant distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of the channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate that the fluctuations in average gate capacitance, circuit gain, 3 db bandwidth and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 62.6%, 22.2%, 63.1% and 41.4%, respectively. Consequently, such a lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors.
Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants
(2010-04-01)
Lee, Kuo-Fu
;
Li, Yiming
;
Hwang, Chih-Hong
;
電子工程學系及電子研究所
;
電信工程研究所
Characteristic variability of a transistor is a crucial issue for nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, we explore the asymmetric sketch of the random dopant distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of the channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate that the fluctuations in average gate capacitance, circuit gain, 3 db bandwidth and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 62.6%, 22.2%, 63.1% and 41.4%, respectively. Consequently, such a lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors.
Asymmetric Gate Capacitance and High Frequency Characteristic Fluctuations in 16 nm Bulk MOSFETs Due to Random Distribution of Discrete Dopants
(2008)
Li, Yiming
;
Hwang, Chih-Hong
;
Yeh, Ta-Ching
;
電信工程研究所
;
Institute of Communications Engineering
Characteristic fluctuation dependence on discrete dopant for 16nm SOI FinFETs at different temperature
(2007)
Li, Yiming
;
Hwang, Chih-Hong
;
Yu, Shao-Ming
;
Huang, Hsuan-Ming
;
Yeh, Ta-Ching
In this paper, we numerically study the discrete-dopant-induced characteristic fluctuations in 16nnn silicon-on-insulator (SOI) FinFETs. For devices under different temperature condition, discrete dopants are statistically generated and positioned into the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Electrical characteristics' fluctuations are growing worse when the substrate temperature increases, the standard deviation of threshold voltage increases 1.75 times when substrate temperature increases from 300K to 400K for example. This "atomistic" device simulation technique is computationally cost-effective and provides us an insight into the problem of discrete-dopant-induced fluctuation and the relation between the fluctuation and thermal effect.
Characteristics Variability of Novel Lateral Asymmetry Nano-MOSFETs due to Random Discrete Dopant
(2009)
Lee, Kou-Fu
;
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Li, Yiming
;
電信工程研究所
In nanoscale silicon FETs, the lateral asymmetric channel (LAC) devices with higher channel doping concentration near the source-end have shown better control of the short channel effects. However, such asymmetric doping profile may introduce different fluctuations in device characteristics. In this paper, the asymmetric sketch of random dopants distribution near source and drain sides in 16 nm bulk MOSFETs' channel is explored. Discrete dopants distributed near-source end and near-drain end of channel region induce rather different fluctuations of gate capacitance and high frequency characteristics. The proposed inverse lateral asymmetry doping profile can effectively suppress both the DC and high frequency characteristic fluctuations, which may benefit the design of sub-20-nm MOSFETs.
Comprehensive Examination of Threshold Voltage Fluctuations in Nanoscale Planar MOSFET and Bulk FinFET Devices
(2008)
Hwang, Chih-Hong
;
Cheng, Hui-Wen
;
Yeh, Ta-Ching
;
Li, Tien-Yeh
;
Huang, Hsuan-Ming
Intrinsic fluctuations on device characteristics, such as the threshold voltage (V(th)) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced Vth fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO(2) for the 1.2 and 0.8 nm EOTs, Al(2)O(3) for the 0.4 nm EOT and HfO(2) for the 0.2 nm EOT) are then for the first time compared with the results of 16nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property. Result of this study confirms the suppression of Vth fluctuations with the gate oxide thickness scaling (using high-kappa dielectric). It's found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device's scaling and have potential in the nanoelectronics application.
DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit
(2009-04-01)
Li, Yiming
;
Hwang, Chih-Hong
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電信工程研究所
;
Institute of Communications Engineering
Silicon-based nanowire field effect transistors (FETs) are potentially next-generation candidates for achieving high-performance targets of the International Roadmap for Semiconductors due to their superior reduction of the short-channel effects and excellent compatibility with planar complementary metal oxide semiconductor (CMOS) fabrication process. In this work, we for the first time numerically explore the dc baseband and high-frequency characteristics, and the design of the device aspect ratio (channel length/channel thickness) for the silicon nanowire FET circuits by using a three-dimensional device/circuit-coupled mixed-mode simulation technique. With the experimentally validated simulation approach, the result shows the rather prolific dc baseband and high-frequency properties of silicon-based nanowire FET devices as active components. In design of silicon nanowire FETs, taking the nanowire's radius and channel length as two crucial factors, the demands of the device aspect ratio on dc characteristics are found to be inversely proportional to the demands of the high-frequency characteristics. Therefore, to compromise both the dc and high-frequency characteristics, the design margin of the device aspect ratio restricted, in which the requirements of dc and high-frequency characteristics provide aspect ratio upper and lower bounds, respectively. Moreover, the design margin will be more tightened for a device with larger radius due to the weakened channel controllability. The extensive results and analyses are presented for the promising devices for the design of high-frequency analog applications.
Discrete Dopant Induced Characteristic Fluctuations in 16nm Multiple-Gate SOI Devices
(2007)
Li, Yiming
;
Hwang, Chih-Hong
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Huang, Hsuan-Ming
;
Yeh, Ta-Ching
;
電信工程研究所
Discrete Dopant Induced Electrical and Thermal Fluctuation in Nanoscale SOI FinFET
(2007)
Li, Yiming
;
Hwang, Chih-Hong
;
Yu, Shao-Ming
;
Huang, Hsuan-Ming
;
電信工程研究所
The International Roadmap for Semiconductors has forecasted a transition from conventional bulk device to silicon-on-insulator (SOI) one, and then to multiple-gate SOI for high-performance devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, the discrete dopant induced electrical and thermal fluctuation of 16nm SOI FinFETs is for the first time explored. A three-dimensional atomistic" device simulation with quantum hydrodynamic equation is proposed and performed for electrical and thermal characteristics of the discrete dopant fluctuated SOI FinFETs. Discrete dopants are statistically positioned in the 3D channel region to study associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Effect of the discrete-dopant-number- and discrete-dopant-position-induced fluctuations on device characteristic including variations of the lattice and electron temperatures are advanced. The large-scale computational statistics study provides us an insight into the fluctuation of electrical and thermal characteristics and mechanism of immunity against fluctuation in SOI FinFETs.
Discrete-dopant-fluctuated threshold voltage roll-off in sub-16 nm bulk fin-type field effect transistors
(2008-04-01)
Li, Yiming
;
Hwang, Chih-Hong
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電信工程研究所
;
Institute of Communications Engineering
The effect of the number and position of discrete dopants on device characteristics is crucial in determining the behavior of nanoscale semiconductor devices. We explore the fluctuations of threshold voltage (V(th)) roll-off in nanoscale bulk fin-type field effect transistors (FinFETs) by a three-dimensional (3D) statistically full-scale "atomistic" device simulation technique. The explored devices are of three different dimensions: 16, 22, and 30 nm(3). Discrete dopants are statistically positioned into the 3D channel region to explore associated carrier transport characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". For the device with a gate length of 16 nm, the V(th) fluctuation of FinFETs is only half that of planar metal-oxide-semiconductor (MOS) FET. Compared with planar MOSFETs, the bulk FinFETs can significantly suppress the fluctuation of V(th) roll-off. The standard deviation of V(th) is proportional to (WL)(-0.25), which is better than the (WL)(-0.5) of planar devices. The superior immunity against fluctuation and the stable fluctuation of V(th) roll-off indicate the bulk FinFET to be a promising device for the sub-16 nm technology era.
Discrete-Dopant-Fluctuated Transient Behavior and Variability Suppression in 16-nm-Gate Complementary Metal-Oxide-Semiconductor Field-Effect Transistors
(2009-04-01)
Li, Yiming
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Hwang, Chih-Hong
;
Cheng, Hui-Wen
;
電信工程研究所
;
Institute of Communications Engineering
Variability in the characteristics of nanoscale complementary metal-oxide-semiconductor (CMOS) field-effect transistors is a major challenge to scaling and integration. However, little attention has been focused on the existence of transient behavior fluctuations of devices owing to random dopant placement. In this study, we explore the discrete-dopant-induced transient behavior fluctuations of 16-nm-gate CMOS circuits through a three-dimensional large-scale statistically sound "atomistic" device-circuit-coupled simulation approach, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". For a 16-nm-gate CMOS inverter, a 3.5% variation of the rise time, a 2.4% variation of the fall time, an 18.3% variation of the high-to-low delay time, and a 13.2% variation of the low-to-high delay time are estimated and discussed. Fluctuation suppression techniques proposed from the device and the circuit viewpoints are implemented to examine the associated intrinsic fluctuations. (C) 2009 The Japan Society of Applied Physics
Discrete-dopant-induced characteristic fluctuations in 16 nm multiple-gate silicon-on-insulator devices
(2007-10-15)
Li, Yiming
;
Hwang, Chih-Hong
;
電信工程研究所
;
Institute of Communications Engineering
The impact of the number and position of discrete dopants on device characteristics is crucial in determining the behavior of nanoscale semiconductor devices. This study explores discrete-dopant-induced characteristic fluctuations in 16 nm single-, double-, triple-, and (square shape) surrounding-gate silicon-on-insulator (SOI) devices. Discrete dopants are statistically positioned in the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation." An experimentally validated simulation was conducted to investigate the threshold voltage (V-th) fluctuation and the variation of the on- and off-state currents of the four explored structures. The fluctuations of V-th of the double-, triple- and surrounding-gate devices are 2.2, 3.3 and 4 times smaller, respectively, than that of planar SOI. Results of this study provide further insight into the problem of fluctuation and the mechanism of immunity against fluctuation in ultrasmall field effect transistors (FETs) with vertical channel structures, such as fin-typed FETs. (C) 2007 American Institute of Physics.
Discrete-Dopant-Induced Power-Delay Characteristic Fluctuation in 16 nm Complementary Metal-Oxide-Semiconductor with High Dielectric Constant Material
(2010)
Han, Ming-Hung
;
Li, Yiming
;
Hwang, Chih-Hong
;
傳播研究所
;
電機工程學系
In this work, we carry out an experimental validated three-dimensional "atomistic'' device-circuit coupled simulation to study the discrete-dopant-induced power and delay fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits. The equivalent gate oxide thicknesses (EOTs) of planar CMOS range from 1.2 nm to 0.2 nm. SiO(2) is used at gate oxide thicknesses of 1.2 and 0.8 nm, Al(2)O(3) at an EOT of 0.4 nm, and HfO(2) at an EOT of 0.2 nm. Under the same device threshold voltage, as EOT decreases from 1.2 to 0.2 nm, the fluctuations of threshold voltage and gate capacitance for CMOS transistors are reduced by 43 and 55%, respectively. For the state-of-art nanoscale circuits using high-dielectric constant (high-kappa) materials, the delay time fluctuation is suppressed significantly from 0.1 to 0.03 ps. For the power characteristics, although the nominal powers of circuits using high-kappa dielectrics are increased owing to the increased EOT, the fluctuations of dynamic power, short circuit power, and static power are reduced by 40, 70, and 30%, respectively. (C) 2010 The Japan Society of Applied Physics
Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit
(2009-05-01)
Li, Yiming
;
Hwang, Chih-Hong
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Li, Tien-Yeh
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電信工程研究所
;
Institute of Communications Engineering
As the dimensions of semiconductor devices continue to be reduced, device fluctuations have become critical to determining the accuracy of timing in circuits and systems. This brief studies the discrete-dopant-induced timing characteristic fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits using a 3-D "atomistic" coupled device-circuit simulation. The accuracy of the simulation has been confirmed by using the experimentally calibrated transistor physical model. For a 1.6-nm-gate CMOS inverter, 3.5%, 2.4%, 18.3%, and 13.2% normalized fluctuations in the rise time, fall time, high-to-low delay time, and low-to-high delay time, respectively, are found. Random dopants may cause significant timing fluctuations in the studied circuits. Suppression approaches that are based on the circuit and device design viewpoints are implemented to examine the associated characteristic fluctuations. The use of shunted transistors in the circuit provides similar suppression to the use of a device with doubled width. However, both approaches increase the chip area. To eliminate the need to increase the chip area, channel engineering approaches (vertical and lateral) are proposed, and their effectiveness in reducing the timing fluctuation is demonstrated.
Doping profile and Ge-dose optimization for silicon-germanium heterojunction bipolar transistors
(2009-10-01)
Li, Yiming
;
Chen, Ying-Chieh
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Hwang, Chih-Hong
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傳播研究所
;
電子工程學系及電子研究所
The speed of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) has been dramatically increased. It is known that the speed of HBTs is dominated by the base transit time, which could be influenced by the doping profile in the base region and the Ge concentration. In this study, the design of the doping profile and Ge-dose concentration for SiGe HBTs are mathematically formulated and solved by a technique of geometric programming ( GP). The solution calculated by the GP method is guaranteed to be a global optimal. The accuracy of the adopted numerical optimization technique is first confirmed by comparing with two-dimensional device simulation. The result of this study shows that a 23% Ge fraction may maximize the current gain; furthermore, a 12.5% Ge may maximize the cut-off frequency for the explored device, where a 254 GHz cut-off frequency is achieved.
Effect of fin angle on electrical characteristics of nanoscale round-top-gate bulk FinFETs
(2007-12-01)
Li, Yiming
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Hwang, Chih-Hong
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電信工程研究所
;
Institute of Communications Engineering
In this brief, electrical characteristics of 25-nm round-top-gate fin-typed field-effect transistors (FinFETs) on silicon wafers are numerically explored. With an ideal fin angle (i.e., theta = 90 degrees), the FinFETs with doped and undoped (for this case, the device has a metal gate) channels that was fabricated on silicon and silicon-on-insulator wafers are simulated and compared. With a 3-D quantum-correction-transport simulation, characteristic comparison shows that bulk FinFETs with the undoped channel possess promising electrical characteristics. By considering different short-channel effects, dependence of the device performance on the nonideal fin angle and fin height is further investigated. Optimal structure configuration for the round-top-gate bulk FinFETs is thus drawn to show the strategy of fabrication in sub-25-mn MOSFET devices.
Effect of Flash Lamp Annealing and Laser Spike Annealing on Random Dopant Fluctuation of 15-nm Metal-Oxide-Semiconductor Devices
(2012-03-01)
Cheng, Hui-Wen
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Hwang, Chih-Hong
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Chao, Ko-An
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Li, Yiming
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材料科學與工程學系
Comparison of two different implantation processing techniques for random dopant (RD)-induced threshold voltage fluctuation (sigma V-th) in 15-nm metal-oxide-semiconductor (MOS) devices is reported. Implantations of flash lamp annealing and laser spike annealing are simulated using a kinetic Monte Carlo (KMC) technique. The KMC generated distributions are mapped into device channel for three-dimensional quantum mechanical transport simulation to estimate threshold voltage fluctuation. The main results of this study show that the laser spike annealing could achieve 30% reduction of RDF-induced sigma V-th for low-power application of 15-nm MOS devices, compared with flash lamp annealing.
Effect of Process Variation on 15-nm-Gate Stacked Multichannel Surrounding-Gate Field Effect Transistor
(2009)
Han, Ming-Hung
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Cheng, Hui-Wen
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Hwang, Chih-Hong
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Li, Yiming
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傳播研究所
Stacked multichannel transistor architectures were proposed recently which possess very attractive electrical characteristics on low leakage current and high driving current per layout area. However, due to complex manufacturing process, the process variation effect is inevitable and whose impact is unknown. Therefore, this study investigates the impact of process variation on 15-nm-gate stacked multichannel transistors consisting of the gate length deviation, channel position variation, quadruple-shaped channel structure and elliptic gate oxide. Our preliminary result shows that the stacked multichannel devices have good immunity to the gate length deviation and channel spacing variations; however, they are sensitive to the gate coverage ratio and gate oxide thickness variations. This study provides an insight into the device characteristic variations, which may benefit the development of nanoscale stacked multichannel transistors and circuits.
Effect of Single Grain Boundary Position on Surrounding-Gate Polysilicon Thin Film Transistors
(2007)
Li, Yiming
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Huang, Jung Y.
;
Lee, Bo-Shian
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Hwang, Chih-Hong
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電信工程研究所
In this paper, single-grain-boundary-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e, gate-all-around, GAA) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of single grain boundary near the drain side has an ill effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of threshold voltage can be reduced from 15 % to 5 %, with varying of gate structures of the GAA polysilicon TFT.
Effect of UV illumination on inverted-staggered a-Si : H thin film transistors
(2007)
Li, Yiming
;
Lou, Jen-Chung
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Chen, Chung-Le
;
Hwang, Chih-Hong
;
Yan, Shuoting
The hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's) have been widely used as switching devices for large-area electronics, such as active matrix liquid crystal displayers. Effect of UV Illumination on improving device switching characteristics has been experimentally observed and studied. However, the inside mechanisms including state and density of traps, are not clear yet. In this work, to characterize the optimal device characteristics, we thus solve a set of Poisson, electron/hole continuity, and lattice heat flow equations coupling with density and distribution of trap states in the a-Si:H layer. The I-V characteristics of the inverted staggered a-Si:H TFT's with different magnitude of UV light illumination is for the first time calculated and carefully calibrated with experimental measured data. It is found that the traps states in the a-Si:H layer and the movement of Fermi level from the conduction band after UV illumination. This study provides an insight into the effect of UV illumination and the mechanism to improve the switching characteristics of a-Si TFTs.