Browsing by Author "JEN, CW"

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A LOW-COST RASTER ENGINE FOR VIDEO GAME, MULTIMEDIA PC AND INTERACTIVE TV
(1995-08-01)
CHEN, CL
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LIANG, BS
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JEN, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A low-cost Raster Engine (RE) is designed and implemented to improve the performance of 3D computer graphics and image composition application for video games, multimedia PCs and interactive TVs. Three operation modes: Gouraud and Phong shading algorithms, and image composition are incorporated in this chip. Modified digital differential analyzer (DDA), 2-level pipeline, and constant execution time for calculating cos(n) theta are proposed as the features of this design. The accelerator is implemented by 0.8 um SPDM CMOS VLSI technology and able to release more then 50% CPU loads.
A low-cost raster engine for video game, multimedia PC and interactive TV
(1995-01-01)
CHEN, CL
;
LIANG, BS
;
JEN, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A NEW ARRAY ARCHITECTURE FOR PRIME-LENGTH DISCRETE COSINE TRANSFORM
(1993-01-01)
GUO, JI
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LIU, CM
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JEN, CW
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資訊工程學系
;
電子工程學系及電子研究所
A new approach to derive a systolic algorithm for prime-length discrete cosine transform (DCT) is proposed. It makes use of the input/output (I/O) data permutations and the symmetry property of cosine kernels such that the proposed array possesses outstanding performance in hardware cost of the processing elements (PE's), average computation time, and the I/O cost.
A NOVEL CORDIC-BASED ARRAY ARCHITECTURE FOR THE MULTIDIMENSIONAL DISCRETE HARTLEY TRANSFORM
(1995-05-01)
GUO, JI
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LIU, CM
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JEN, CW
;
資訊工程學系
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電控工程研究所
In this paper, a coordinate rotation digital computer (CORDIC)-based array architecture is presented for computing the multidimensional (M-D) discrete Hartley transform (DHT). Since the kernel of the M-D DHT is inseparable, the M-D DHT problems cannot be computed through the 1-D DHT's directly. Bracewell et al. have presented an algorithm for the M-D DHT through the 1-D DHT's. The existing hardware architectures have been designed using this algorithm. However, the postprocessing required in the algorithm leads to high hardware overhead. This paper presents a new algorithm to compute M-D DHT through a special 1-D transform which is derived through considering both the separable computation and the efficient implementation with CORDIC architectures. This algorithm provides a direct way to compute the M-D DHT separably through 1-D transforms with simpler postprocessing than that in Bracewell's approach. Also, the algorithm exploits the symmetry of the triangular functions to reduce the computational complexity. Using this algorithm, we design an array architecture for the M-D DHT. This architecture features a systolic computing style, PE's with a CORDIC structure, low I/O cost, and the encapsulated new M-D DHT algorithm.
A NOVEL MEMORY ARCHITECTURE FOR VIDEO SIGNAL PROCESSOR
(1993)
HUNG, JS
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LIN, CH
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JEN, CW
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電控工程研究所
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Institute of Electrical and Control Engineering
A NOVEL VLSI ARRAY DESIGN FOR THE DISCRETE HARTLEY TRANSFORM USING CYCLIC CONVOLUTION
(1994-01-01)
GUO, JI
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LIU, CM
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JEN, CW
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交大名義發表
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National Chiao Tung University
A PARALLEL ADAPTIVE ALGORITHM FOR MOVING TARGET DETECTION AND ITS VLSI ARRAY REALIZATION
(1992-11-01)
LIU, CM
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JEN, CW
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
The application of an innovations-based detection algorithm (IBDA) in moving target detector (MTD) radars has been shown to be efficient. In this correspondence, an adaptive algorithm for the IBDA is derived. This algorithm behaves well in numerical properties and computational complexity. Also, it possesses high computing parallelism and data locality which lead to the feasibility of VLSI array realization. A systolic array is designed with the iteration time being (2n + 1) and the number of processing elements being [(n2 + 3n)/2], where n is the length of the adaptive filter.
A RASTER ENGINE FOR COMPUTER GRAPHICS AND IMAGE COMPOSITION
(1994)
CHEN, CL
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LIN, CH
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LEE, HR
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JEN, CW
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電子工程學系及電子研究所
BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERING
(1993-09-01)
LEE, CL
;
JEN, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A class of selection algorithms by binary partition is very efficient for median and rank order filtering. A unified discussion of these algorithms is presented. Binary partition algorithms have better time-area complexity than sorting methods. Counting, firing, and updating are three basic steps. A generic structure is proposed to realize these algorithms. They can be implemented by simple and regular modules in VLSI.
BIT-SLICED MEDIAN FILTER DESIGN BASED ON MAJORITY GATE
(1992-02-01)
LEE, CL
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JEN, CW
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
There are arithmetic problems for the hardware realisation of bit-level median filtering algorithms. A design of a majority gate which is composed of output-wired inverters is proposed. The area and time complexities are better than the digital and analogue designs now available. This circuit is applied to a median filter design which is based on majority selection, the computation problems are thus avoided. It is a bit-sliced architecture with constant cycle time. Window shapes can be arbitrarily changed through mask-and-set modules. A median filtering system for two-dimensional image processing is presented. A binary majority gate is also an essential element in decision-making circuitry which is applied in fault-tolerant computing systems, artificial neural networks or related applications.
CMOS THRESHOLD GATE AND NETWORKS FOR ORDER STATISTIC FILTERING
(1994-06-01)
LEE, CL
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JEN, CW
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電控工程研究所
;
Institute of Electrical and Control Engineering
The threshold gate is a very good candidate in the realization of order statistic filtering. In this brief paper, a simple procedure is developed to determine the circuit parameters for a set of output-wired CMOS inverters in order to implement threshold functions for order statistic filtering. Weighted and nonweighted order statistic filters in either binary or integer domain can be easily realized in similar architectures. An incremental scheme is also proposed to construct threshold gate networks for general or multi-stage order statistic filters.
DATA FLOW REPRESENTATION OF ITERATIVE ALGORITHMS FOR SYSTOLIC ARRAYS
(1992-03-01)
JEN, CW
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KWAI, DM
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
An algebraic representation is proposed for regular iterative algorithms that can be described as bundles of data flows with different wavefronts. Modeling data flows with a generating function of power series, this form corresponds to the geometric representation such as a dependence graph. The main attributes of systolic algorithms and arrays are revealed by a unique data flow representation. This provides the ability to pipeline two or more systolic arrays solving different subproblems without intermediate buffering. We use an example to show the case with which our technique can be used.
DEPLETION WIDTHS OF THE METAL-INSULATOR SEMICONDUCTOR (MIS) STRUCTURE
(1981)
JEN, CW
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LEE, CL
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LEI, TF
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
DESIGN OF A SYSTOLIC ARRAY SYSTEM FOR LINEAR STATE-EQUATIONS
(1988-10-01)
JOU, SJ
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JEN, CW
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
DESIGN OF ALGORITHM-BASED FAULT-TOLERANT VLSI ARRAY PROCESSOR
(1989-11-01)
LIU, CM
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JEN, CW
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
DESIGN OF ONE-DIMENSIONAL SYSTOLIC-ARRAY SYSTEMS FOR LINEAR STATE-EQUATIONS
(1990-06-01)
JEN, CW
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JOU, SJ
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
EFFICIENT TIME-DOMAIN SYNTHESIS OF PIPELINED RECURSIVE FILTERS
(1994-09-01)
LAN, CP
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JEN, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
An efficient technique is developed for the synthesis of pipelined recursive filters directly from the time domain specifications. Based on the modified least-squares approximation, the pipelinable denominator form that contains only the powers of z(-R) is designed inherently by expressing the design criterion in terms of only the nonzero denominator coefficients and a final design is derived. Due to the lack of the conventional transformation overheads, the multiplications needed are fewer in the resulted filters. Moreover, we introduce a new kind of companion matrix that characterizes the stable properties of pipelined recursive filters. Using this result, we prove that the proposed direct synthesis method can always guarantee the stability.
ELLIPSOMETRY MEASUREMENTS ON SIO2-FILMS FOR THICKNESSES UNDER 200-A
(1987-09-01)
HO, JH
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LEE, CL
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JEN, CW
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LEI, TF
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交大名義發表
HARDWARE SHARING IN TREE-STRUCTURE QMF BANKS
(1994)
LEE, HR
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JEN, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
MOTA - A MOSFET TIMING SIMULATOR
(1986-10-01)
JOU, SJ
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JEN, CW
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SHEN, WZ
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LEE, CL
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交大名義發表