Browsing by Author "Jen, CW"

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A bandwidth and memory efficient MPEG-4 shape encoder
(2004)
Lee, KB
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Chang, NYC
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Chin, HY
;
Hsu, HC
;
Jen, CW
We have developed a shape encoder hardware for MPEG-4 video coding. On the one hand, the alpha component is compressed and therefore, the size and memory access of alpha frame memory can be reduced to 50% and 56.25% respectively. On the other hand, an efficient data transfer scheme combining the run length coding and addressing mode can reduce average data transfer time to 9.39% and accelerate the shape encoding process. The shape encoder can support MPEG-4 Main Profile at Level 4 in real-time. In addition, verification and testing methods are also considered.
A compact DSP core with static floating-point arithmetic
(2006-02-01)
Lin, TJ
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Lin, HY
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Chao, CM
;
Liu, CW
;
Jen, CW
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) components with the host microprocessor. This paper presents a compact DSP for multi-core systems, which is fully programmable and has been optimized to execute a set of signal processing kernels very efficiently. The DSP core was designed concurrently with its automatic software generator based on high-level synthesis. Moreover, it performs lightweight arithmetic-the static floating-point (SFP), which approximates the quality of floating-point (FP) operations with the hardware similar to that of the integer arithmetic. In our simulations, the compact DSP and its auto-generated software can achieve 3X performance (estimated in cycles) of those DSP cores in the dual-core baseband processors with similar computing resources. Besides, the 16-bit SFP has above 40 dB signal to round-off noise ratio over the IEEE single-precision FP, and it even outperforms the hand-optimized programs based on the 32-bit integer arithmetic. The 24-bit SFP has above 64 dB quality, of which the maximum precision is identical to that of the single-precision FP. Finally, the DSP core has been implemented and fabricated in the UMC 0.18 mu m 1P6M CMOS technology. It can operate at 314.5 MHz while consuming 52mW average power. The core size is only 1.5 mmx1.5 mm including the 16 KB on-chip memory and the AMBA AHB interface.
A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization
(2004)
Lee, KB
;
Hsu, HC
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an efficient VLSI architecture of shape-adaptive discrete cosine transform (SA-DCT) for MPEG-4. The proposed architecture contains a cost-effective 1-D variable-length DCT engine and an auto-aligned transpose memory organization. Compared to other designs for SA-DCT, our architecture requires fewer multipliers whereas has higher throughout. Together with address generators and address pointers, the auto-aligned transpose memory organization can achieve transposing, shifting and aligning simultaneously without saving shape information. When clocking at 66.7 MHz, the proposed architecture has a throughput of 43.83 Mpixels/sec.
A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding
(2004)
Lee, KB
;
Lin, JY
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
MPEG-4 shape coding comprises context-based arithmetic encoding (CAE) as its centerpiece. Since the CAE algorithm has complicated coding procedure and strong data dependency, it is hard to exploit its pipeline and parallel facilities. This paper presents a fast dual symbol CAE that runs at a higher clock rate whereas requires less clock cycle count for encoding. The proposed design is based on the unique characteristics of shape information as well as the numerical properties of the probabilities indexed by the contexts, and it is capable of encoding either a singe symbol or two symbols within each clock cycle. Together with the adaptive predication for the order of coding process, redundant operations can be skipped and therefore the average clock cycles for each coding process is improved by a factor of 1.72. Furthermore, the probability table is rearranged to reduce critical path delay. When synthesized from Verilog RTL design by using TSMC 0.35mum 1P4M CMOS technology, the design with I/O pads occupies an area of 2528 x 2520 mum(2) and is capable of running at 100 MHz.
A hardware-efficient architecture for 3-D graphics processor
(1995)
Liang, BS
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Nieh, YC
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Niou, YP
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Jen, CW
;
Chuang, G
In 3-D graphics processor, large associated information per pixel cause storage and bus transfer problems in pixel operations. In this paper, we explore the parallelisms in pixel information to design a hardware-efficient architecture, hence the hardware cost of redundant registers in pipeline stages and unnecessary bus transfer can be saved.
A high performance carry-save to signed-digit recoder for fused addition-multiplication
(2000)
Yeh, WC
;
Jen, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we will present a carry-save to signed-digit (CS2SD) receder with high performance and small area. The recoder can be employed in common fused addition-multiplication operation which is widely used in various signal-processing applications. Our design shows 18% area-time product improvement over the traditional designs.
A memory efficient realization of cyclic convolution and its application to discrete cosine transform
(2003)
Chen, HC
;
Guo, JI
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a memory efficient design for realizing the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic computation, and exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel and then separate the kernel to be two perfect cyclic forms to facilitate an efficient realization of 1-D N-point DCT using (N-1)/2 adders or substractors, one small ROM module, a barrel shifter, and N-1/2 + 1 accumulators. The comparison results with the existing designs show that the proposed design can reduce delay-area product significantly.
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform
(2005-03-01)
Chen, HC
;
Guo, JI
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Chang, TS
;
Jen, CW
;
電子工程學系及電子研究所
This paper presents a memory-efficient approach to realize the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic (DA) computation, exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel, separate the kernel to be two perfect cyclic forms, and partition he content of ROM into groups to facilitate an efficient realization of a one-dimensional (1-D) N-point DCT kernel using (N-1)/2 adders or substractors, one small ROM module, a barrel shifter, and ((N - 1)/2) + 1 accumulators. The proposed memory-efficient design technique is characterized by rearranging the content of the ROM using the conventional DA approach into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DCT outputs for increasing the ROM utilization. Considering an example using 16-bit coefficients, the proposed design can save more than 57% of the delay-area product, as compare with the existing DA-based designs in the case of the 1-D seven-point DCT. Finally, a 1-D DCT chip was implemented to illustrate the efficiency associated with the proposed approach.
A multiplierless reconfigurable resizer for multi-window image display
(1997-01-01)
Huang, CM
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Chang, TS
;
Jen, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a real-time resizing IC that can dynamically reconfigure the multiplierless polyphase CIC (cascaded-integer-comb) filter modules to meet even non-integer resizing ratio. The IC can process four 320x200 30 frames/sec at 55 Mhz clock.
A multiplierless reconfigurable resizer for multi-window image display
(1997-08-01)
Huang, CM
;
Chang, TS
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a real-time resizing IC that can dynamically reconfigure the multiplierless polyphase CIC (cascaded-integer-comb) filter modules to meet even noninteger resizing ratio. The hardware cost is greatly reduced by using overlap-save based block input and concurrent register reset scheme. The simulated results show that this chip can process four 320x200 30 frames/sec at 55 MHz clock.
A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding
(2005-02-01)
Lee, KB
;
Lin, JY
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
MPEG-4 shape coding comprises context-based arithmetic encoding (CAE) as its centerpiece. Since the CAE algorithm has a complicated coding procedure and strong data dependency, it is hard to exploit its pipeline and parallel facilities. Furthermore, to encode multiple symbols within one, clock cycle, it needs to overcome the issues of extracting multiple contexts of these symbols, deriving multiple probabilities from these contexts, and performing multiple multiplicative range update operations. This paper presents an efficient pipelined multisymbol CAE architecture for real-time MPEG-4 shape encoding. The proposed design is based on the inherent characteristics of binary alpha blocks as well as the numerical properties of the probabilities indexed;by the contexts, and it is capable of encoding either a singe symbol, or multiple symbols within each clock cycle. To overcome the aforementioned issues under the consideration of the hardware cost and the critical path delay, only symbols with a particular set of contexts are chosen to be processed simultaneously within the same clock cycle. Theoretical analysis shows that the majority of symbols have contexts belonging to this particular set, and therefore CAE processing can be significantly accelerated. An example VLSI implementation of proposed architecture that encodes two symbols within each clock cycle without sacrificing the clock rate can achieve a speedup of 1.47 in comparison with traditional CAE architectures. This particular two-symbol design can support MPEG-4 Main Profile at levels 3 and 4 under extreme and typical conditions, respectively. When synthesized from Verilog RTL design by using TSMC 0.35-mum 1P4M CMOS technology, the design can run at 90 MHz.
A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers
(2000)
Hsiao, IYL
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Jen, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
With the advent of world wide web and the services on it, there is a strong demand for the nodes that make internet routing with guaranteed speed and throughput. Current 40-channel WDM (Wavelength Division Muitiplexing) has boosted a single 2.5Gbps OC-48 link to 100Gbps, so the requirement to make IPv4 (Internet Protocol version 4) routing table lookup is 100MLPS (million lookups per second). The emerging 96-channel WDM and 10Gbps OC-192 fibers certainly demand much more. Previous works on East IPv4 routing table lookup used indirect RAM indexing or CPU caching or CAM (Content Addressable Memory) to achieve a few or tens MLPS. Their theoretical best performances depend on the memory access speed and some of them are not extensible to accommodate the forthcoming IPv6. In this paper we describe a novel way to do this work with only a FPGA. And this approach, which utilize the logic modeling and minimization techniques, promises a capability to make IPv4 (and IPv6) routing decisions in a pipelined fashion within only a FPGA CLB delay time.
A new hardware-efficient architecture for programmable FIR filters
(1996-09-01)
Lee, HR
;
Jen, CW
;
Liu, CM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Although much research has been done on efficient high-speed filter architectures, much of this work has focused on filters with fixed coefficients, such as Canonical Signed Digit coefficient filter architectures, multiplierless designs, or memory-based designs. In this paper, we focus on digit-serial, high-speed architectures with programmable coefficients. To achieve high performance goals, we consider both of algorithm level and architecture implementation level of FIR filters. In algorithm level, we reformulate the FIR formulation in bit-level and take the associative property of the addition in both the digit-serial multiplications and filter formulations. In architecture level, we considered issues to implement the reformulated results efficiently. The issues include addition implementation, data flow arrangements, and treatment of sign-extensions. Based on the above considerations, we can obtain a fitter architecture with accumulation-free tap structure and properties of short latency, flexible pipelinability and high speed. Comparing the cost and performance with previous designs, we find that the proposed architecture reduces the hardware cost of a programmable FIR filter to only half that of previous designs without sacrificing performance.
A new hardware-efficient architecture for programmable FIR filters
(1996-09-01)
Lee, HR
;
Jen, CW
;
Liu, CM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Although much research has been done on efficient high-speed filter architectures, much of this work has focused on filters with fixed coefficients, such as Canonical Signed Digit coefficient filter architectures, multiplierless designs, or memory-based designs. In this paper, we focus on digit-serial, high-speed architectures with programmable coefficients. To achieve high performance goals, we consider both of algorithm level and architecture implementation level of FIR filters. In algorithm level, we reformulate the FIR formulation in bit-level and take the associative property of the addition in both the digit-serial multiplications and filter formulations. In architecture level, we considered issues to implement the reformulated results efficiently. The issues include addition implementation, data flow arrangements, and treatment of sign-extensions. Based on the above considerations, we can obtain a fitter architecture with accumulation-free tap structure and properties of short latency, flexible pipelinability and high speed. Comparing the cost and performance with previous designs, we find that the proposed architecture reduces the hardware cost of a programmable FIR filter to only half that of previous designs without sacrificing performance.
A novel recursive digital filter based on signed digit distributed arithmetic
(1997)
Su, CL
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Hwang, YT
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Jen, CW
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交大名義發表
;
電子工程學系及電子研究所
In this paper, we adopt the Signed Digit (SD) number system and the Distributed Arithmetic (DA) computing scheme to achieve a novel design of high throughput recursive digital filters. The SD system enables a carry-propagation free addition as well as the most-significance-digit (MSD) first computation. Based on these properties, we devise a recursive computing scheme which successfully reduces the initiation interval to the delay of computing one digit instead of the entire word. Combined with the DA scheme, we can further exploit the bit-level parallelism while maintain a low circuit complexity. We design a Signed Digit Multi-Operand Adders (SDMA) array as the building block to implement the SD-DA algorithm. It can compute an inner product operation efficiently and suit well to VLSI implementation.
A novel register organization for VLIW digital signal processors
(2005)
Lin, TJ
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Lee, CC
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Liu, CW
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Jen, CW
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電子工程學系及電子研究所
This paper presents a novel register organization for VLIW DSPs. The simulation results show the performance of a DSP with the proposed register file is comparable with state-of-the-art DSPs. However, the proposed register file can save 89.7% area of a conventional centralized one, while reducing its access time by 68.6%.
A programmable concurrent video signal processor
(1996)
Chen, CC
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Jen, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A simple processor core design for DCT/IDCT
(2000-04-01)
Chang, TS
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Kung, CS
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Jen, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a cost effective processor core design that features the simplest hardware and is suitable for discrete cosine transform/indiscrete cosine transform (DCT/IDCT) operations in H.263 and digital camera. This design combines the techniques of fast direct two dimensional DCT algorithm, the bit-level adder-based distributed arithmetic, and common subexpression sharing;to reduce the hardware cost and enhance the computing speed. The resulting architecture is very simple and regular such that it can be easily scaled for higher throughput rate requirements. The DCT design has been implemented by 0.6 mu m SPDM CMOS technology and only costs 1493 gate count, or 0.78 mm(2), The proposed design can meet real-time DCT/IDCT requirements of H.263 codec system for QCIF image frame size at 10 frames/s with 4:2:0 color format. Moreover, the proposed design still possesses additional computing power for other operations when operating at 33 Mhz.
An architecture of full-search block matching for minimum memory bandwidth requirement
(1998)
Tuan, JC
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Jen, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper art architecture of full-search block matching motion estimation suitable for high qualify video is proposed. Minimum memory bandwidth is an important requirement in motion estimation architecture especially when dealing with high quality video such as large frame size video. Memory bandwidth wilt increase to an unrealistically high value without careful consideration, which no cost efficient solution can afford it, This architecture is designed for overcoming the frame memory bandwidth bottleneck by exploiting the maximum data reuse property. This is done bf setting up local memory for storing frame data. The size of local memory is also optimized to near minimum value only little overhead is introduced. Due to the reduction of memory bandwidth, the costs of frame memory modules, I/O pin count and the power consumption can be reduced but 100% hardware efficiency if still achieved Simple and regular interconnections is featured to ensure high speed operation by an efficient and distributed local memory organization.
An area and time efficient adder for multiple additions with different word-length
(1997)
Liang, BS
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Nieh, YC
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Jen, CW
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交大名義發表
;
電子工程學系及電子研究所
To calculate multiple independent additions with different word-length by hardware sharing, we propose a new adder architecture in this paper, named self carry routing adder (SCRA). Multiple additions for data with different precision are usually occurring in some applications, like DDA operation in 3-D graphics rendering. By segmentation, rearrangement and dynamic carry routing, SCRA design can effectively decrease the delay time, reduce hardware area, and achieve high hardware utilization.