Browsing by Author "Jeng, Erik S."

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Effect of ZnSe partial capping on the ripening dynamics of CdSe quantum dots
(2007-02-19)
Lai, Y. J.
;
Yang, C. S.
;
Chen, W. K.
;
Lee, M. C.
;
Chang, W. H.
The ripening dynamics of CdSe quantum dots (QDs) partially capped with ZnSe layer are investigated. Atomic force microscopy (AFM) images show that the ripening of QDs is dramatically accelerated by depositing a ZnSe partial capping layer. The driving force of ripening enhancement is attributed to the increasing strain energy with capping thickness. For a ZnSe partial capping layer of below 3 ML, photoluminescence exhibits a clear redshift with increasing ZnSe monolayers. It is attributed to the size of the CdSe QD increases with ZnSe partial capping, in a manner that is consistent with the results of the AFM study. (c) 2007 American Institute of Physics.
Implementation of Surface Acoustic Wave Vapor Sensor Using Complementary Metal-Oxide-Semiconductor Amplifiers
(2009-04-01)
Chiu, Chia-Sung
;
Chang, Ching-Chun
;
Ku, Chia-Lin
;
Peng, Kang-Ming
;
Jeng, Erik S.
A surface acoustic wave (SAW) vapor sensor is presented in this work. A SAW delay line oscillator on quartz substrate with the high gain complementary metal-oxide-semiconductor (CMOS) amplifier using a two-poly-two-metal (2P2M) 0.35 mu m process was designed. The gain of the CMOS amplifier and its total power consumption are 20 dB and 70 mW, respectively. The achieved phase noise of this SAW oscillator is -150 dBc/Hz at 100 kHz offset. The sensing is successfully demonstrated by a thin poly(epichlorohydrin) (PECH) polymer film on a SAW oscillator with alcohol vapor. This two-in-one sensor unit includes the SAW device and the CMOS amplifier provides designers with comprehensive model for using these components for sensor circuit fabrication. Furthermore it will be promising for future chemical and biological sensing applications. (C) 2009 The Japan Society of Applied Physics
Investigation of programming charge distribution in nonoverlapped implantation nMOSFETs
(2006-10-01)
Jeng, Erik S.
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Kuo, Pai-Chun
;
Hsieh, Chien-Sheng
;
Fan, Chen-Chia
;
Lin, Kun-Ming
Novel gate-to-drain nonoverlapped-implantation (NOI) nMOSFETs have been developed as potential multibit-per-cell nonvolatile-memory (NVM) devices. The lateral charge distribution of the NOI NVM device programmed by channel hot electron injection is investigated by charge-pumping (CP) techniques with presumed interface trap distributions. For the first time, the CP results have revealed the lateral charge distribution and trapping density at the NOI's programmed state. The maximum trapping charge density locates near its drain junction. The charge distribution is estimated about 90 nm in length and spread widely over the NOI region. Two-dimensional simulators with charge bars using the same charge trapping distribution confirm the experimental results by fitting their I-DS - V-G curves.
Performance improvement and scalability of nonoverlapped implantation nMOSFETs with charge-trapping spacers as nonvolatile memories
(2007-12-01)
Jeng, Erik S.
;
Chiu, Chia-Sung
;
Hon, Chih-Hsueh
;
Kuo, Pai-Chun
;
Fan, Chen-Chia
This paper explores gate-to-source/drain nonoverlapped implantation (NOI) devices that function as nonvolatile memories (NVMs) by trapping charges in the silicon nitride spacers. These NOI nMOSFET devices with improved NVM characteristics were simulated and demonstrated. For a 0.8 V shift in the threshold voltage, the programming and erasing speeds of NOI devices are as fast as 40 and 60 mu s, respectively. Improvements of other related NVM characteristics, including charge retention and cycling endurance,, are reported. Finally, the scalability of NOI devices is simulated and discussed.