Browsing by Author "Jou, Chewn-Pu"

Now showing 1 - 7 of 7

A 0.55THz Y-Vector Network Configured Beam Steering Phased Array in CMOS Technology
(2018-01-01)
Zhao, Yan
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Al Hadi, Richard
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Lu, Hsin-Chia
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Tseng, Tzu-Shiuan
;
Zhang, Yan
A Y-vector oscillator network is devised to configure (sub)-mm-wave/terahertz (THz) beamforming systems with minimized footprint and energy consumption. It requires no traditional adjustable phase shifter at multi-channel front end which usually suffer from high insertion loss at these frequencies. A compact (1.4mm(2)) CMOS 1x4 Beam Steering Phased Array (BSPA) based on this network is validated at 0.55THz with +/- 30 degrees steering angle range. This is the first monolithic BSPA reported beyond 0.5THz.
A 38mW 40Gb/s 4-Lane Tri-Band PAM-4 / 16-QAM Transceiver in 28nm CMOS for High-Speed Memory Interface
(2016)
Cho, Wei-Han
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Li, Yilei
;
Du, Yuan
;
Wong, Chien-Heng
;
Du, Jieqiong
Compact and Low-Loss ESD Protection Design for V-Band RF Applications in a 65-nm CMOS Technology
(2012)
Chu, Li-Wei
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Lin, Chun-Yu
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Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.
Design of ESD Protection Cell for Dual-Band RF Applications in a 65-nm CMOS Process
(2012)
Chu, Li-Wei
;
Lin, Chun-Yu
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Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
An ESD protection cell consisted of a diode, a silicon-controlled rectifier (SCR), a PMOS, and inductors was proposed for dual-band radio-frequency (RF) ESD protection. The proposed ESD protection cell was suitable for RF circuit designers for them to easily apply ESD protection in the dual-band RF circuits.
ESD Protection Design for Radio-Frequency Integrated Circuits in Nanoscale CMOS Technology
(2013-01-01)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
Nanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection on circuit performances, ESD protection at input/output pads must be carefully designed. In this work, a new proposed ESD protection design has been realized in a nanoscale CMOS process. Experimental results of the test circuits have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.
ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process
(2014)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
;
Tseng, Jen-Chou
All wireless communication products must meet the reliability specifications during mass production. To prevent from electrostatic discharge (ESD) damages, the ESD protection designs must be added at all input/output pads in chip. Some ESD protection designs with low parasitic capacitance for radio-frequency (RF) applications are reviewed in this paper. Besides, a novel ESD protection design is proposed and realized in a 65nm CMOS process to protect the wideband RF circuits. In this work, diodes are used for ESD protection and inductors are used for high-frequency performance fine tuning. Experimental results of the test circuits have been successfully verified.
ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process
(2012)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
;
Jou, Chewn-Pu
To protect radio-frequency (RF) integrated circuits from electrostatic discharge (ESD) damages, silicon-controlled rectifier (SCR) devices have been used as main on-chip ESD protection devices due to their high ESD robustness and low parasitic capacitance in nanoscale CMOS technologies. In this work, the SCR device assisted with an inductor to resonate at the selected frequency band for RF performance fine tune was proposed. Besides, the inductor can be also designed to improve the turn-on efficiency of the SCR device for ESD protection. Verified in a 65-nm CMOS process, the ESD protection design with the inductor-triggered SCR for 60-GHz RF applications can achieve good RF performances and high ESD robustness.