Browsing by Author "Jou, Christina F."

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2.45GHz/5.2GHz switched dual-band CMOS LNA with 4 gain control modes
(2005)
Chang, Win-Ming
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Cheng, Kuo-Hua
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Jou, Christina F.
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傳播研究所
;
Institute of Communication Studies
A switched dual-band low noise amplifier with four gain control modes operating at the 2.45-GHz/5.2GHz has been simulated based on a 0.18-um TSMC CMOS process. This dual-band LNA with two input channels and each tuned to 2.45GHz and 5.2GHz separately, by switching the output resonator inductor on/off, the input transistors are enabled/disabled for band selection. A novel gain control scheme is introduced, and this gain control scheme is low in circuit complexity. The four gain control modes are executed by turning on/off the four shunted NMOS at the output of this cascode topology, and the four gain modes can be controlled digitally to adapt to the received RF signals. Compared with the current literatures, this novel gain control scheme not only have high gain control range in both bands, but also have reasonable noise figure in the low gain mode even with 12-dB power gain lower than the high gain mode. The P1dB of the proposed LNA in the low gain mode is 13dB higher than the one in the high gain mode in both bands. The peak of the input and output return loss is locked in band in each gain mode which is an important feature of this proposed LNA. In the high gain mode, the LNA approaches 22-dB maximum power gain and 2.67 DSB noise figure at 2.45GHz. In the 5.2-GHz band, the maximum power gain is 15-dB and the DSB noise figure is 2.47-dB. The gain can be switched by 12-dB between the high gain and the low gain mode at 2.45-GHz and 5.2-GHz.
3-8 GHz broadband low power mixer
(2008)
Chen, Chih-Hau
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Jou, Christina F.
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傳播研究所
;
Institute of Communication Studies
A 3-8 GHz broadband mixer is presented in this paper. This broadband mixer is low power and high conversion gain. It provides current reuse and ac-coupled folded switching. This mixer is designed in TSMC 0.18-mu m CMOS technology. This broadband mixer achieves simulated conversion gain of 9 +/- 1.5 dB, a single sideband noise figure lower than 15.2 dB and IIP3 batter than -7 dBm. From 3-8 GHz, at supply voltage of 1.5 V power consumption without output buffer is 3.27 mW and power consumption with buffer is about 8 mW. The chip area is 1079 mu m x 761 mu m.
77-110 GHz 65-nm CMOS Power Amplifier Design
(2014-05-01)
Wu, Kun-Long
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Lai, Kuan-Ting
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Hu, Robert
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Jou, Christina F.
;
Niu, Dow-Chih
This paper details the development of our millimeter-wave wideband power amplifier design. By treating the power combiner as an impedance transformer which allows different loading impedance to be taken into account, a compact wideband power-combining network can be constructed. With small transmission-line attenuation being sustained and maximum output power easily extracted from the transistors over the 77-110 GHz frequency range, a power amplifier can then be designed using 65-nm CMOS process to cover the whole W-band. In the on-wafer measurement, the gain is around 18 dB, the output reflection coefficients is below -10 dB, and the output-referred 1 dB compression point can reach 12 dBm at 1.2 V bias condition; when the bias is increased to 2.5 V, a 18 dBm output power is recorded. To our knowledge, this is the first CMOS power amplifier that covers the whole W-band.
77GHz Power Amplifier Design Using WIN 0.1 mu m GaAs pHEMT Process
(2014-01-01)
Lai, Kuan-Ting
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Wu, Kun-Long
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Hu, Robert
;
Jou, Christina F.
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交大名義發表
This paper reports our 77GHz power-amplifier designs using WIN 0.1 mu m GaAs pHEMT process provided by the commercial WIN foundry. The first two stages of the power amplifier is made of common-source transistors for gain amplification, and then followed by two-and four-paralleled transistors where the 3dB two-way Wilkinson power splitters/combiners for large output power delivery are used. All the by-pass capacitors for drain and gate biases have been optimized to have small series impedance at W-band. The input DC-blocking capacitor is made coupled lines, which also functions as tuning circuit. With 2.5V and 350mA drain bias, the small-signal gain is 12dB, as measured on-wafer at room temperature; the output-referred 1dB compression point is 6dBm. With 3dBm input power, the saturated output power is around 8.6dBm. Good input- and output-port matching has also been observed. The chip size is 1000x2500 mu m(2) and it consumes 875mW.
A 0.75 VCMOS low-noise amplifier for ultra wide-band wireless receiver
(2007)
Wu, Hui-I.
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Hsiung, Zi Hao
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Jou, Christina F.
;
傳播研究所
;
Institute of Communication Studies
An ultra-wideband (UWB) CMOS low-noise amplifier(LNA) topology that combines a common-gate stage for input wideband matching with a shunt-peaked folded-cascode configuration for wideband amplifying stage is presented in this paper. The proposed UNVB LNA achieves simulated power gain > 10dB from 3.3 to 10.1 GHz with only 0.75 V supply using 0.18 mu m CMOS process. Its broadband matching is better than -10 dB for S11 and S22 from 3.1 to 10.6 GHz, and an average noise figure is about 4 dB, while consuming 11.5 mw with output buffer amplifier.
A 1-V, Low-Power CMOS LNA for Ultra-wideband Receivers
(2007)
Chang, Po Yang
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Wu, Hui-I
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Jou, Christina F.
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電信工程研究所
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Institute of Communications Engineering
A 1-V, low-power ultra-wideband (UWB) low-noise amplifier (LNA) for IEEE 802.153a is implemented in TSMC 0.18-mu m. mixed signal/RF CMOS process. With only 1V bias voltage, the LNA can achieve a measured flat power gain (S21) of 10dB from 2.5 to 8.5 GHz while consuming only 7.25 mW. The minimum noise figure is 3.46dB. A simplified Chebyshev filter is used to achieve an input broadband matching of a measured S11 < -7.1dB from 3.1 to 10.6 GHz. An output-matching buffer is designed specially to match for high gain at upper frequency, the measured S22 is <-12.5dB from 3.1 GHz to 10.6 GHz. Furthermore, the high frequency electromagnetic effect of the transmission lines is considered in this circuit.
A 10 GHz low power CMOS quadrature voltage-controlled oscillator
(2005)
Tarng, Shih-Hao
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Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
A 10 GHz low power CMOS quadrature voltage-controlled oscillator (QVCO) realized with LC-tank is presented. The QVCO is fabricated by TSMC 0.18 mu m 1P6M CMOS process. Based on the simulation results, this circuit draws 7.52 mA current from 1.8 V power supply. The total power consumption is 13.54 mW including the buffer. The tuning range is 730 MHz (about 7.3%) and the phase noise is - 103.44 dBc/Hz @ 1 MHz offset at 10 GHz. Compared with the recent proposed works by using the power-frequency-normalized figure of merit (FOM), it shows a better phase noise performance and lower power consumption..
A 24/60GHz Dual-Band Millimeter-Wave On-Chip Monopole Antenna Fabricated with a 0.13-mu m CMOS Technology
(2009)
Huang, Jie-Huang
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Wu, Jin-Wei
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Chiou, Yi-Lin
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Jou, Christina F.
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電信工程研究所
A 24 / 60GHz dual-band millimeter-wave on-chip antenna fabricated in TSMC 0.13-mu m CMOS process is presented here. We design the feeding network by using the coplanar waveguide (CPW) structure. For the dual-band design, there are two major current paths to radiate. To avoid the harmonic frequency band of the low frequency-band, we add two strips to couple the harmonic frequency of the low frequency-band. Besides, the two strips let the higher frequency-band performance better. At this work, the simulator is based 3-D full-wave EM solver, Ansoft HFSS. The on-chip antenna size is 0.76 x 1.045 mm(2). The bandwidth of the lower band and higher is about 180MHz and 700MHz, respectively. The simulated gain is about -9dB for 24GHz and about 1 dB for 60GHz
A 3-8 GHz RF Receiver Front-End for Multi-Band UWB Wireless System
(2007)
Hsiung, Zi-Hao
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Wu, Hui-I
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Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
This paper demonstrates a RF receiver front end circuit for multi-band orthogonal frequency division multiple access (MB-OFDM) using standard 0.18um complementery metal oxide semiconductor (CMOS) technology. The receiver front end includes a low-noise amplifier and a down conversion mixer. The proposed LNA uses transistor's intrinsic capacitor Cgd and only one inductor as input matching network to achieve wideband impedance matching. And the proposed mixer uses folded current reused architecture to decrease supply voltage and enhance conversion power gain effectively. This wideband front end circuit achieves 19-21.5 dB of power gain and 4-3-6.2 dB of double-sideband (DSB) noise figure from 3.1GHz to 8 GHz with IF=100 MHz. The simulated core current consumption was 13.1 mA from a 1.5 V supply, with a compact size of 1.16 mm(2).
A 5.15-5.825 GHz high-gain and low-noise CMOS down-conversion mixer with low-power for WLAN 802.11a
(2013-01-01)
Dai, Yu-Hsiu
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Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
This paper presents a 5.15GHz-5.825GHz CMOS down-conversion mixer with high-gain, low-noise, and low-power for WLAN 802.11a receiver. The cascade topology is adopted at the transconductance stage to improve power gain and reduce noise factor. And the inductive peaking technique is implemented at the switching stage to flatten the frequency bandwidth of conversion gain. This mixer is implemented in TSMC 0.18 mu m CMOS process, and the chip size including the test pads is 1.2mm(2). The proposed mixer offers a measured conversion gain from 26.2 to 26.7dB, a flat DSB noise figure from 7.3 to 8dB with IF 10MHz, and input third-order intercept point from 8 to -12dBm, over the whole working range, while consuming 11.32mW from a 1.8V supply voltage.
A calibrated direct conversion front-end transmitter with resonant matching techniques for mobile WiMAX/WiBro applications
(2012-05-01)
Chang, Chia-Hung
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Jou, Christina F.
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電機工程學系
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Department of Electrical and Computer Engineering
A direct conversion front-end transmitter with the properties of high linearity and high single sideband rejection ratio is described in this paper. The transmitter employs two resonant matching techniques to improve its operating bandwidth. The first resonant circuit design is applied at the inter-stage of the LO input buffer in order to achieve a wideband frequency response which ranges from dc to 6 GHz. The second resonant circuit is applied at the power amplifier (PA) driver output stage to increase the matching bandwidth and meet both the Worldwide Inter-operability for Microwave Access (WiMAX) and Wireless Broadband (WiBro) applications simultaneously. In addition, the sideband signal and carrier leakage of this transmitter are further minimized by a proposed calibration circuit design to achieve the error vector magnitude (EVM) specifications. The measured single sideband performance with calibration mechanism demonstrates approximately 15 dB improvement on sideband and carrier suppression. The rejected sideband and carrier signals can be up to 55.19 and 56.31 dBc, respectively. The measured dynamic gain range of the transmitter is 53 dB in 1-dB step with a maximum relative gain error lower than 0.4 dB. The transmitter delivers +0.766 dBm output power with EVM of -34.687 dB for the orthogonal frequency division multiple access (OFDMA) 64QAM-3/4 modulated signals. The measured constellation is minimized to be < 1.5% with output power from -2.3 to -36.2 dBm.
A CMOS low-noise amplifier with impedance feedback for ultra-wideband wireless receiver system
(2008)
Huang, Zhe-Yang
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Huang, Che-Cheng
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Chen, Chun-Chieh
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Hung, Chung-Chih
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Jou, Christina F.
In this paper, a CMOS low-noise amplifier (LNA) is designed for ultra-wideband (UWB) wireless receiver system. The design consists of a wideband input impedance matching network, a cascoded amplifier with shunt-peaked load, a RLC-impedance feedback loop and an output buffer for measurement purpose. It is fabricated in TSMC 0.18um standard RF CMOS process. The LNA gives 11.5dB maximum power gain between 3.1GHz-5.0GHz while consuming 5.7mW through a 1.8V supply voltage. Over the 3.1GHz-5.0GHz frequency band, the minimum noise figure (NF) is 4.7dB. Input return loss lower than -12.7 dB in all bandwidth have been achieved.
A Colpitts Current-Reused QVCO Based on Capacitor Coupling
(2011)
Lai, Hsing-Han
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Shen, I-Shing
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Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
This paper presents a Colpitts current-reused quadrature voltage-controlled oscillator (QVCO) based on capacitor coupling in TSMC 0.18um CMOS 1P6M process technology. Comparing to conventional parallel-coupled QVCO (P-QVCO), the proposed QVCO achieves a better phase noise and phase accuracy. The proposed QVCO operates from 4.57GHz to 5.02GHz. The measured phase noise at 1MHz offset frequency is -119 dBc/Hz and the measured phase error of quadrature signals arc 5 at 5CHz. With 1.8V power supply, the power consumption is 8.46mW. The figure of merit (FOM) of proposed QVCO is 183.7 dBc/Hz. The die area is 1x0.78mm(2)
A Compact Wideband Leaky-Wave Antenna With Etched Slot Elements and Tapered Structure
(2010-07-01)
Wu, Jin-Wei
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Jou, Christina F.
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Wang, Chien-Jen
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電信工程研究所
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Institute of Communications Engineering
A compact wideband leaky-wave antenna (LWA) with etched slot elements and tapered structure is studied. The proposed antenna is composed of an asymmetric-fed multi-section tapered short leaky-wave antenna with two embedded slots and a ground plane with etched slot elements. Base on the concept of LWA, the asymmetric-fed is utilized to excite the first higher order mode. By etching slot elements on the ground plane, the current distribution of this antenna can be influenced to compact the width of conventional LWA. In order to achieve the impedance matching, this multi-section tapered short leaky-wave antenna is embedded with two rectangular slots. This technique not only improves the impedance matching but also suppresses the back lobe. According to the measured results, the impedance bandwidth achieves about 1.30 GHz for 7-dB return loss, which covers the range from 3.30 to 4.60 GHz, and the scanning angle of the measured main beam is about 36 degrees, which covers the range from 17 degrees to 53 degrees. This short LWA is only about 1.14 lambda(0) 3.4 GHz, and the back lobe can be suppressed by 7.5 dB at 4.3 GHz. Due to the etched slot elements on the ground plane, the frequency of the radiation angle is shifted to lower frequency by 750 MHz, which can compact the width of LWA by more than 20%.
A DC-20GHz CMOS Active Power Divider Design
(2010-01-01)
Huang, Jing-Ying
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Wu, Hui-I
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Hu, Robert
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Jou, Christina F.
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Niu, Dow-Chi
We report the design of a wideband active power divider using commercial CMOS process. This circuit is made of two distributed amplifiers sharing a common input artificial transmission line while two distinct transmission lines are employed for the output ports. Since the input transmission line tends to be overly capacitive now when compared with the conventional distributed amplifier, the constituting gain cells need to be revised so as to retain the intended 20GHz bandwidth. Small input and output reflection coefficients have been observed, and the measured output port isolation is below -30dB across the whole bandwidth, which is beyond the reach of passive power dividers. Magnitude and phase imbalances of the two output ports are 0.2dB and 0.4 degrees at 15GHz and 0.9dB and 0.6 degrees at 20GHz. The noise figure is 6.9dB at 15GHz and 9.4dB at 20GHz. The input-referred 1dB compression point is -9.5dBm at 15GHz and -10.5dBm at 20GHz. With the bias of 2.5Volt and 64Amp, the total power dissipation is 160mWatt.
A Direct Conversion Merged LNA-I/Q-Mixer With Noise Reduction Using Dual Cross Coupling for WiMAX/WiBro Applications
(2012-01-01)
Chang, Chia-Hung
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Jou, Christina F.
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電機工程學系
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Department of Electrical and Computer Engineering
A direct conversion merged low noise amplifier (LNA) and I/Q-mixer with new noise reduction technique is presented in this letter. The merged LNA-I/Q-mixer employs a dual capacitor cross coupling (CCC) technique to improve the circuit noise performance. The first CCC is applied at the transconductance stage of the LNA to increase the effective transconductance, which in turn lowers the noise figure and decreases the current consumption. The second CCC connection is applied at the cascode stage of the LNA, which can reduce the influence of the noise current from cascode transistors. The simulation shows the proposed combination of the LNA and I/Q-mixer configuration with the dual CCC technique can achieve NF 3 dB better than that of conventional merged topologies in a wideband application. The measured NF is lower than 4.55 dB from 2.3 to 2.7 GHz. In addition, low-power and low-cost circuit is realized due to current-reused and inductor-less design at the interface of the LNA and I-Q mixer. The core circuit only consumes 16.83 mW and occupies 0.16 mm(2) area.
A Dual-Band Circularly-Polarized Antenna with Double C Shape Strips
(2011)
Lin, Yi-Mao
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Huang, Jie-Huang
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Jou, Christina F.
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電信工程研究所
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Institute of Communications Engineering
A new design of dual-band circular polarized antenna is presented. The proposed antenna is achieved using microstrip-fed with two circular strips and two circular patch. One circular strip radiates lower band, the other one covers higher band. By adding the circular patch on the back of the substrate, the left-hand circular polarization (LHCP) gain at the positive z axial of this proposed antenna has been improved. The antenna operates in two bands which are 2.5GHz and 5.2GHz. These two operating bands can be applied for the WiMax and WLAN application. Experimental results show the proposed antenna has good return loss and circular polarization characteristics. The 10 dB return loss impedance bandwidths for the lower band (2.5GHz) and higher band (5.2GHz) are 50% and 23%, respectively. The 3dB axial-ratio bandwidth are 14.8% and 4.0% with respect to 2.5GHz and 5.2GHz, respectively.
A dual-band concurrent RF front-end receiver design for GPS and Bluetooth applications
(2005)
Chen, Po-Da
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Chen, Cheng-Hung
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Chang, Win-Ming
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Cheng, Kuo-Hua
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Jou, Christina F.
This paper presents a new concurrent dual-band radio frequency receiver front-end design that is intended for Globe Positioning System (GPS) and Bluetooth applications. A low IF architecture is chosen for low-cost and low-power purpose. Using a dual-band sub-harmonic mixer make this new concurrent dual-band receiver architecture requires only a single frequency synthesizer in order the chip area could be reduced. This concurrent frequency synthesizer only needs to provide 0.784GHz and 1.24GHz local frequency signals in this dual-band topology. This receiver is operated at 1.8V, and the simulation shows a voltage gain of 27.7dB at 1.57GHz and 24.2dB at 2.45GHz, a noise figure of 4.13dB at 1.57GHz and 6.84dB at 2.45GHz with a total power consumption of 22.2mW.
A Folded Current-Reused Down-Converter Mixer for Ultra Wide-Band Applications
(2007)
Hsiung, Zi-Hao
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Wu, Hui-I
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Jou, Christina F.
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電信工程研究所
;
Institute of Communications Engineering
This paper demonstrates an ultra-wideband mixer using TSMC 0.18 um mixed-signal/RF CMOS 1P6M technology. The main idea is to replace the traditional common source trans-conductance stage with a folded current-reused pair. It can enhance conversion power gain effectively without additional power consumption. And the folded approach is used to reduce supply voltage. To achieve wideband frequency response, second-order LC ladder wideband input matching network is utilized. This wide-band mixer achieves measured conversion power gain of 13.5-15.5 dB and a DSB noise figure of 11-14.5 dB from 3.1GHz to 8 GHz. The dc power consumption is 11.25 mW under a supply voltage of 1.5 V, with a compact sin of 0.83 mm(2).
A highly Integrated SiGeBiCMOS Class F Power Amplifier for Bluetooth Application
(2006-01-01)
Chen, Jia-Liang
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Chiu, Tang-Jung
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Jou, Christina F.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A highly integrated 2.4-GHz Class F power amplifier using TSMC 0.35 mu m 3P3M standard SiGe BiCMOS process is presented. This amplifier integrates both the input matching network and output fundamental and third harmonic loading networks onto the chip. Additional fine tuning output circuit is implemented outside the chip for some flexibility. Measurement results show that the power amplifier can exhibit an output power about 20dBm, with power added efficiency (PAE) of 34.2% at 2.4-GHz Bluetooth frequency band. This result demonstrates the potential of full-scale integration of the high efficiency power amplifier.