Browsing by Author "Ker, Ming-Dou"

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2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue
(2008)
Ker, Ming-Dou
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Wang, Tzu-Ming
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Liao, Hung-Tai
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電機學院
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College of Electrical and Computer Engineering
A new 2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without suffering gate-oxide reliability issue is proposed, which is one of the key mixed-voltage I/O cells in a cell library. The proposed circuit is realized with only thin gate-oxide devices with floating n-well technique. The proposed 2xVDD-tolerant crystal oscillator circuit has been designed and verified in a 90-mn 1-V CMOS process to serve 1/2-V mixed-voltage interface applications.
2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Low Standby Leakage in 65-nm CMOS Process
(2010)
Lin, Chun-Yu
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Ker, Ming-Dou
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電機學院
;
College of Electrical and Computer Engineering
With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only similar to 200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.
A 13.56 MHZ METAMATERIAL FOR THE WIRELESS POWER TRANSMISSION ENHANCEMENT IN IMPLANTABLE BIOMEDICAL DEVICES
(2019-01-01)
Chen, Kuan-Jung
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Chen, Wei-Ming
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Tan, Li-Yang
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Cheng, Yu-Ting
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Ker, Ming-Dou
This paper presents a 13.56MHz metamaterial for wireless power transmission (WPT) enhancement in implantable biomedical devices based on the evanescent wave coupling mechanism. The power transmission efficiency (PTE) will increase from 46 to 51% with the metamaterial while the transmitting and receiving antennas are placed with a 1 cm distance and lcm offset horizontal misalignment, will increase from 39 to 46% with the metamaterial while the two antenna planes are placed at a distance of 1.5 cm with an axial offset of 15, and will increase from 28 to 50% with two pieces of metamaterial placed with a 0.5cm distance while the two antenna planes are placed with a 1.5 cm distance and 1 cm offset horizontal misalignment.
A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process
(2009-05-01)
Hsiao, Yuan-Wen
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Ker, Ming-Dou
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Two electrostatic discharge (ESD)-protected 5-GHz differential low-noise amplifiers (LNAs) are presented with consideration of pin-to-pin ESD protection. The pin-to-pin ESD issue for differential LNAs is addressed for the first time in the literature. Fabricated in a 130-nm CMOS process, both ESD-protected LNAs consume 10.3 mW under 1.2-V power supply. The first LNA with double-diode ESD protection scheme exhibits the power gain of 17.9 dB and noise figure of 2.43 dB at 5 GHz. Its human-body-model (HBM) and machine-model (MM) ESD levels are 2.5 kV and 200 V, respectively. With the same total parasitic capacitance from ESD protection devices, the second LNA with the proposed double silicon-controlled rectifier (SCR) ESD protection scheme has 6.5-kV HBM and 500-V MM ESD robustness, 17.9-dB power gain, and 2.54-dB noise figure at 5 GHz. The ESD test results have shown that the pin-to-pin ESD test is the most critical ESD-test pin combination for the conventional double-diode ESD protection scheme. With the proposed double-SCR ESD protection scheme, the pin-to-pin ESD robustness can be significantly improved without degrading RF performance. Experimental results have shown that the ESD protection circuit for LNA can be co-designed with the input matching network to simultaneously achieve excellent ESD robustness and RF performance.
A 70nW, 0.3V Temperature Compensation Voltage Reference Consisting of Subthreshold MOSFETs in 65nm CMOS Technology
(2016)
Lu, Ting-Chou
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Ker, Ming-Dou
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Zan, Hsiao-Wen
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電子工程學系及電子研究所
;
光電工程學系
Being operated with 0.3V supply voltage in a standard 65nm CMOS process, a new CMOS temperature compensated voltage reference circuit is proposed with subthreshold transistors and native nMOS. The reference drain current provided by the gate voltage of a subthreshold nMOS output transistor is nearly independent of temperature due to the existence of mutual compensation of mobility and threshold voltage variation. The new proposed temperature compensated voltage reference circuit functions well with the output voltage VREF of 168 mV at room temperature as no extra laser trimming is needed after fabrication. The total power consumption is about 70nW. With the VDD power supply of 0.3V, the temperature coefficient (TC) of voltage reference circuit is 105 ppm/degrees C as temperature varies from -20 degrees C to 100 degrees C. The chip size of the fabricated bandgap reference circuit is 0.0053mm(2).
A 8 Phases 192 MHz Crystal-Less Clock Generator with PVT Calibration
(2017-01)
Lu, Ting-Chou
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Ker, Ming-Dou
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Zan, Hsiao-Wen
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Liu, Jen-Chieh
;
Lee, Yu
A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18pm CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65 mu m x 75 mu m and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/degrees C from 0 to 100 degrees C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58-ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192 MHz within 12.67k-hits. At 192 MHz, it shows a 1-MHz-offset phase noise of -102 dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively.
A 8 Phases 192 MHz Crystal-Less Clock Generator with PVT Calibration
(2017-01)
Lu, Ting-Chou
;
Ker, Ming-Dou
;
Zan, Hsiao-Wen
;
Liu, Jen-Chieh
;
Lee, Yu
A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18pm CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65 mu m x 75 mu m and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/degrees C from 0 to 100 degrees C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58-ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192 MHz within 12.67k-hits. At 192 MHz, it shows a 1-MHz-offset phase noise of -102 dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively.
A BENDING N-WELL BALLAST LAYOUT TO IMPROVE ESD ROBUSTNESS IN FULLY-SILICIDED CMOS TECHNOLOGY
(2010)
Wen, Yong-Ru
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Ker, Ming-Dou
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Chen, Wen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.
A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic Hearing
(2017-01-01)
Qian, Xin-Hong
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Wu, Yi-Chung
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Yang, Tzu-Yi
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Cheng, Cheng-Hsiang
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Chu, Hsing-Chien
In this paper, a bone-guided cochlear implant (BGCI) SOC microsystem is proposed and designed. The BGCI microsystem uses four or more electrodes placed on the bone surface of the cochlea and one on the round window to preserve partially the acoustic hearing. The external SOC of the BGCI processes the acoustic signals and generates stimulation patterns and command that are transmitted to the implanted chip through the 13.56MHz wireless power and bidirectional data telemetry. The implanted chip with 4-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 mu A and sends back the power indication and electrode impedance error signals to the external SOC. Electrical tests on the fabricated BGCI has been performed. The in-vivo animal tests on guinea pigs has shown the evoked Wave III of EABR waveforms. The proposed BGCI can be applied to patients with high-frequency hearing loss, tinnitus, and dizziness.
A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
(2017-07-01)
Nidhi, Karuna
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Ker, Ming-Dou
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25-mu m bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage (V-P) and the zero-bias drain current (I-DS0) of the proposed n-JFET device can be modified by adjusting the P+ separation (L) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of I-D-V-D and I-D-V-G.
A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18-mu m 1.8-V/3.3-V Low-Voltage CMOS Process
(2017-10-01)
Luo, Zhicong
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Ker, Ming-Dou
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Yang, Tzu-Yi
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Cheng, Wan-Hsueh
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電子工程學系及電子研究所
A new digitally dynamic power supply technique for 16-channel 12-V-tolerant stimulator is proposed and realized in a 0.18-mu m 1.8-V/3.3-V CMOS process. The proposed stimulator uses four stacked transistors as the pull-down switch and pullup switch to withstand 4 times the nominal supply voltage (4 x VDD). With the dc input voltage of 3.3 V, the regulated threestage charge pump, which is capable of providing 11.3-V voltage at 3-mA loading current, achieves dc conversion efficiency of up to 69% with 400-pF integrated capacitance. Power consumption is reduced by implementing the regulated charge pump to provide a dynamic dc output voltage with a 0.5-V step. The proposed digitally dynamic power supply technique, which is implemented by using a p-type metal oxide semiconductor (PMOS) inverter with pulldown current source and digital controller, greatly improves the power efficiency of a system. The silicon area of the stimulator is approximately 3.5 mm(2) for a 16-channel implementation. The functionalities of the proposed stimulator have been successfully verified through animal test.
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control
(2018-11-01)
Cheng, Cheng-Hsiang
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Tsai, Ping-Yuan
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Yang, Tzu-Yi
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Cheng, Wan-Hsueh
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Yen, Ting-Yang
A 16-channel closed-loop neuromodulation system-on-chip (SoC) for human epileptic seizure control is proposed and designed. In the proposed SoC, a 16-channel neural-signal acquisition unit (NSAU), a biosignal processor (BSP), a 16-channel high-voltage-tolerant stimulator (HVTS), and wireless power and bidirectional data telemetry are designed. In the NSAU, the input protection circuit is used to prevent MOSFET from overstressing by the high-voltage stimulations. Hence, NSAUs can share electrodes with stimulators. The auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIAs) are designed with the chopper-stabilized technique with a new offset reduction loop. The measured input-referred noise is 2.09 mu V-rms and the noise-efficiency factor (NEF) is 3.78. The entropy-and-spectrum seizure detection algorithm is implemented in the BSP with 0.76-s seizure detection latency and 97.8% detection accuracy. When the seizure onset is detected by the BSP, the HVTS with adaptive supply control delivers 0.5-3-mA biphasic current stimulation to suppress the seizure onset. The proposed SoC is powered wirelessly, and the bidirectional data telemetry is realized through the same pair of coils in 13.56 MHz. The downlink data rate is 211 Kb/s with the binary phase-shift keying (BPSK) modulation and a new BPSK demodulator. The uplink data rate is 106 Kb/s with the load-shift keying (LSK) modulation. The proposed SoC is fabricated in a 0.18-mu m CMOS technology and occupies 25 mm(2). Electrical tests have been performed to characterize the SoC performance. In vivo animal experiments using mini-pigs have been performed to successfully verify the closed-loop neuromodulation functions on epileptic seizure suppression.
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
(2014-01-01)
Chen, Wei-Ming
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Chiueh, Herming
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Chen, Tsan-Jieh
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Ho, Chia-Lun
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Jeng, Chi
An 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, seizure detection, and electrical stimulation in order to suppress epileptic seizures. The SoC is composed of eight energy-efficient analog front-end amplifiers (AFEAs), a 10-b delta-modulated SAR ADC (DMSAR ADC), a configurable bio-signal processor (BSP), and an adaptive high-voltage-tolerant stimulator. A wire-less power-and-data transmission system is also embedded. By leveraging T-connected pseudo-resistors, the high-pass (low-pass) cutoff frequency of the AFEAs can be adjusted from 0.1 to 10 Hz (0.8 to 7 kHz). The noise-efficiency factor (NEF) of the AFEA is 1.77, and the DMSAR ADC achieves an ENOB of 9.57 bits. The BSP extracts the epileptic features from time-domain entropy and frequency spectrum for seizure detection. A constant 30-mu A stimulus current is delivered by closed-loop control. The acquired signals are transmitted with on-off keying (OOK) modulation at 4 Mbps over the MedRadio band for monitoring. A multi-LDO topology is adopted to mitigate the interferences across different power domains. The proposed SoC is fabricated in 0.18-mu m CMOS and occupies 13.47 mm(2). Verified on Long Evans rats, the proposed SoC dissipates 2.8 mW and achieves high detection accuracy 92% within 0.8 s.
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic SoC for Real-Time Epileptic Seizure Control
(2013-01-01)
Chen, Wei-Ming
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Chiueh, Herming
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Chen, Tsan-Jieh
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Ho, Chia-Lun
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Jeng, Chi
A Fully Integrated Closed-Loop Neuromodulation SoC with Wireless Power and Bidirectional Data Telemetry for Real-Time Human Epileptic Seizure Control
(2017-01-01)
Cheng, Cheng-Hsiang
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Tsai, Ping-Yuan
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Yang, Tzu-Yi
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Cheng, Wan-Hsueh
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Yen, Ting-Yang
This paper presents a 16-channel closed-loop neuromodulation SoC for human seizure control. The SoC includes a 16-ch signal acquisition unit, a bio-signal processor, a 16-ch adaptive stimulator, and wireless telemetry. The signal acquisition unit achieves 3.78 NEF and shares electrodes with stimulator. The seizure detection latency is 0.76s and delivered 0.5-3mA biphasic current stimulation. The SoC is powered wirelessly and bidirectional data telemetry is realized through the same pair of coils in 13.56MHz.
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications
(2018-06-01)
Luo, Zhicong
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Ker, Ming-Dou
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電子工程學系及電子研究所
;
生醫電子轉譯研究中心
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Department of Electronics Engineering and Institute of Electronics
A high-voltage-tolerant and power-efficient stimulator with adaptive power supply is proposed and realized in a 0.18- mu m 1.8-V/3.3-V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent issues of electrical overstress and gate-oxide reliability in low-voltage transistors. The on-chip high-voltage generator uses a pulse-skip regulation scheme to generate a variable dc supply voltage for the stimulator by detecting the headroom voltage on the electrode sites. With a dc input voltage of 3.3 V, the onchip high-voltage generator provides an adjustable dc output voltage from 6.7 to 12.3 V at a step of 0.8 V, which results in a maximal system power efficiency of 56% at a 2400-mu A stimulus current. The charge mismatch of the stimulator is down to 1.7% in the whole stimulus current range of 200-3000 mu A. The in vivo experiments verified that epileptic seizures could be suppressed by the electrical stimulation provided by the proposed stimulator. In addition, the reliability measurements verified that the proposed stimulator is robust for electrical stimulation in medical applications.
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process
(2016-12)
Luo, Zhicong
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Ker, Ming-Dou
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電子工程學系及電子研究所
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生醫電子轉譯研究中心
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Department of Electronics Engineering and Institute of Electronics
This paper presents a 4 x V-DD neuro-stimulator in a 0.18-mu m 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000-mu A biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 mu A) The residual average dc current is less than 6.6 nA after shorting operation.
A High-Voltage-Tolerant Stimulator Realized in the Low-Voltage CMOS Process for Cochlear Implant
(2014-01-01)
Lin, Kuan-Yu
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Ker, Ming-Dou
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Lin, Chun-Yu
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生醫電子轉譯研究中心
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Biomedical Electronics Translational Research Center
A biomedical stimulator with four high-voltage-tolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-mu m CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.
A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-mu m 5-V CMOS Process
(2013-05-01)
Huang, Yu-Ching
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Ker, Ming-Dou
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Based on good electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) device is used for on-chip ESD protection. The major concern of SCR is the latch-up issue, because of its low holding voltage. Previous papers tried to design latchup-immune SCR devices; however, those devices would cause lower ESD robustness. In this letter, a new latchup-immune and robust SCR device for ESD protection is proposed and verified in a 0.25-mu m 5-V CMOS process. Through inserting one additional parasitic bipolar junction transistor into SCR device structure, this new proposed SCR can increase the holding voltage without causing degradation on its ESD robustness.
A new architecture for charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes
(2007)
Wang, Tzu-Ming
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Shen, Wan-Yi
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Ker, Ming-Dou
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new architecture of charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes is proposed, which is composed of two identical pumping branches and four-phase clock signals. The four-phase clock signals are designed to have no undesirable return-back leakage path during clock transition and to control the charge transfer MOSFET switches in the proposed circuit to be turned on and off completely. Therefore, its pumping efficiency is higher than that of the conventional one. Because the gate-to-source and gate-to-drain voltages of all devices in the new proposed charge pump circuit do not exceed the normal power supply voltage (VDD), the new proposed charge pump circuit is suitable for applications in low-voltage CMOS processes.