Browsing by Author "Kim, Keunwoo"

Now showing 1 - 5 of 5

An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process
(2008-09-01)
Mukhopadhyay, Saibal
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Kim, Keunwoo
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Jenkins, Keith A.
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Chuang, Ching-Te
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Roy, Kaushik
This paper presents an on-chip characterization method for random variation in minimum sized devices in nanometer technologies, using a sense amplifier-based test circuit. Instead of analog current measurements required in conventional techniques, the presented circuit operates using digital voltage measurements. Simulations of the test structure using predictive 70 nm and hardware based 0.13 mu m CMOS technologies show good accuracy (error similar to 5%-10%) in the prediction of random variation even in the presence of systematic variations. A test chip is fabricated in 0.13 mu m bulk CMOS technology and measured to demonstrate the operation of the test structure.
Optimal design of triple-gate devices for high-performance and low-power applications
(2008-09-01)
Chiang, Meng-Hsueh
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Lin, Jeng-Nan
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Kim, Keunwoo
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Chuang, Ching-Te
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電子工程學系及電子研究所
Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V(T)'s for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.
Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap
(2009-02-01)
Wei, Lan
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Deng, Jie
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Chang, Li-Wen
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Kim, Keunwoo
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Chuang, Ching-Te
We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.
Stable High-Density FD/SOI SRAM with Selective Back-Gate Bias Using Dual Buried Oxide
(2008)
Kim, Keunwoo
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Kuang, Jente B.
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Gebara, Fadi
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Ngo, Hung C.
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Chuang, Ching-Te
TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability
(2009-12-01)
Kim, Keunwoo
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Kuang, Jente B.
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Gebara, Fadi H.
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Ngo, Hung C.
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Chuang, Ching-Te
This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme.